View ST20-GP6_1271835.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1/123 the information in this datasheet is subject to change ? december 1998 preliminary data gps processor ST20-GP6 features n application specific features ? 12 channel gps correlation dsp hardware, st20 cpu (for control and position calculations) and memory on one chip ? no tcxo required ? rtca-sc159 / waas / egnos supported n gps performance ? accuracy - stand alone with sa on <100m, sa off <30m - differential <1m - surveying <1cm ? time to first fix - autonomous start 90s - cold start 45s - warm start 7s - obscuration 1s n enhanced 32-bit vl-risc cpu - c2 core ? 16/33/50 mhz processor clock ? 25 mips at 33 mhz ? fast integer/bit operations n 64 kbytes on-chip sram n 128 kbytes on-chip rom n programmable memory interface ? 4 separately configurable regions ? 8/16-bits wide ? support for mixed memory ? 2 cycle external access n programmable uart (asc) n parallel i/o n vectored interrupt subsystem n diagnostic control unit n power management ? low power operation ? power down modes n professional toolset support ? ansi c compiler/link driver and libraries ? debugging/profiling and simulation tools n technology ? static clocked 50 mhz design ? 3.3 v, sub micron technology n 100 pin pqfp package n jtag test access port applications n global positioning system (gps) receivers n car navigation systems n fleet management systems n time reference for telecom systems gps radio 12 channel gps low controller power real time clock/calendar 64k sram programmable memory interface ST20-GP6 st20 cpu interrupt controller serial communications parallel input/output diagnostic control unit . . . 16 2 uart (asc) hardware dsp 128k optional mask rom test access port 42 1707 02
contents 2/123 ST20-GP6 1 introduction . . . . . . . . . . . . ................................................ 5 2 ST20-GP6 architecture overview . . . . . ...................................... 7 3 digital signal processing module . . . . . . . . . . . . . . . . .......................... 11 3.1 dsp module registers .......................................................................................................... ................. 13 4 central processing unit . . . . . . . . . . . . . ..................................... 19 4.1 registers ................................................................................................................... ............................ 19 4.2 processes and concurrency ..................................................................................................... ............ 20 4.3 priority .................................................................................................................... ............................... 22 4.4 process communications ....................................................................................................... ............... 23 4.5 timers ...................................................................................................................... ............................. 23 4.6 traps and exceptions .......................................................................................................... ................. 24 5 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.1 interrupt vector table ........................................................................................................ ..................... 31 5.2 interrupt handlers ........................................................................................................... ....................... 31 5.3 interrupt latency ............................................................................................................ ........................ 32 5.4 preemption and interrupt priority .............................................................................................. ............ 32 5.5 restrictions on interrupt handlers ............................................................................................. ............ 33 5.6 interrupt configuration registers ............................................................................................. ............... 33 6 interrupt level controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.1 interrupt assignments ........................................................................................................ ................... 37 6.2 interrupt level controller registers ........................................................................................... .............. 37 7 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.1 instruction cycles ........................................................................................................... ....................... 40 7.2 instruction characteristics .................................................................................................. ................... 41 7.3 instruction set tables ........................................................................................................ ..................... 42 8 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ............ 51 8.1 system memory use ............................................................................................................. ................ 51 8.2 boot rom ..................................................................................................................... ........................ 52 8.3 internal peripheral space ..................................................................................................... ................. 52 9 memory subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.1 sram ........................................................................................................................ ........................... 55 9.2 rom ......................................................................................................................... ............................ 55
ST20-GP6 3/123 10 programmable memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10.1 emi signal descriptions ...................................................................................................... ................... 58 10.2 external accesses ........................................................................................................... ...................... 59 10.3 memwait .................................................................................................................... ........................... 60 10.4 emi configuration registers .................................................................................................. ................. 62 10.5 boot source ................................................................................................................. .......................... 65 10.6 default configuration ....................................................................................................... ...................... 65 11 low power controller . . . . . . . . ............................................ 66 11.1 low power control ............................................................................................................ ..................... 66 11.2 low power configuration registers ............................................................................................. ........... 67 12 real time clock and watchdog timer . . . . . . . . . ............................... 70 12.1 power supplies .............................................................................................................. ....................... 70 12.2 real time clock .............................................................................................................. ....................... 70 12.3 watchdog timer .............................................................................................................. ....................... 70 12.4 rtc/wdt configuration registers .............................................................................................. ........... 71 13 system services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ................. 73 13.1 reset, initialization and debug ............................................................................................... ............... 73 13.2 bootstrap .................................................................................................................. ............................ 73 13.3 clocks ..................................................................................................................... .............................. 73 14 diagnostic controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 14.1 diagnostic hardware ......................................................................................................... .................... 75 14.2 access features ............................................................................................................. ....................... 76 14.3 software debugging features .................................................................................................. .............. 77 14.4 controlling the diagnostic controller ......................................................................................... ............. 79 14.5 peeking and poking the host from the target ....................................................................................... .80 14.6 abortable instructions ...................................................................................................... ..................... 80 15 uart interface (asc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 15.1 functionality .............................................................................................................. ............................ 82 15.2 timeout mechanism ........................................................................................................... .................. 85 15.3 baud rate generation ......................................................................................................... ................... 85 15.4 interrupt control ........................................................................................................... ......................... 86 15.5 asc configuration registers .................................................................................................. ................ 88 16 parallel input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ 94 16.1 pio ports0-1 ................................................................................................................ ......................... 94 17 configuration register addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
ST20-GP6 4/123 18 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 19 gps performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ............... 106 19.1 accuracy ................................................................................................................... ............................ 106 19.2 time to first fix ............................................................................................................. ......................... 107 20 timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ............. 108 20.1 emi timings ................................................................................................................. .......................... 108 20.2 reset timings ............................................................................................................... ......................... 110 20.3 pio timings ................................................................................................................. .......................... 111 20.4 clockin timings ............................................................................................................. ........................ 112 20.5 jtag ieee 1149.1 timings ...................................................................................................... ............. 113 21 pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 22 package specifications . . . . . . . . . . . . . . . . . . . . . . . . . ......................... 116 22.1 ST20-GP6 package pinout ...................................................................................................... ............. 116 22.2 100 pin pqfp package dimensions ................................................................................................ ..... 119 23 test access port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 24 device id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .......................... 122 25 ordering information . . . . . . . . ............................................ 122
ST20-GP6 5/123 1 introduction the ST20-GP6 is an application-specific single chip micro using the st20 cpu with microprocessor style peripherals added on-chip. it incorporates dsp hardware for processing the signals from gps (global positioning system) satellites. the twelve channel gps correlation dsp hardware is designed to handle twelve satellites, two of which can be initialized to support the rtca-sc159 specifi cation for waas (wide area augmentation service) and egnos (european geostationary navigation overlay system) services. the ST20-GP6 has been designed to minimize system costs and reduce the complexity of gps systems. it offers all hardware dsp and microprocessor functions on one chip and provides suffi cient on-chip ram and rom. the entire analogue section, rf and clock generation are available on a companion chip. thus, a complete gps system is possible using just two chips, see figure 1.1. figure 1.1 gps system the ST20-GP6 supports large values of frequency offset, allowing the use of a very low cost oscillator, thus saving the cost of a temperature controlled crystal oscillator (tcxo). the cpu and software have access to the part-processed signal to enable accelerated acquisition time. uart dsp asic stb5600 antenna cpu real time clock watchdog ram optional low cost crystal ST20-GP6 parallel i/o single chip no tcxo driver (optional) timer radio mask rom parallel i/o
ST20-GP6 6/123 the ST20-GP6 can implement the gps digital signal processing algorithms using less than 50% of the available cpu processing power. this leaves the rest available for integrating oem application functions such as route-fi nding, map display and telemetry. a hardware microkernel in the st20 cpu supports the sharing of cpu time between tasks without an operating system or executive overhead. the architecture is based on the st20 cpu core and supporting macrocells developed by stmicroelectronics. the st20 micro-core family provides the tools and building blocks to enable the development of highly integrated application specifi c 32-bit devices at the lowest cost and fastest time to market. the st20 macrocell library includes the st20cx family of 32-bit vl-risc (variable length reduced instruction set computer) micro-cores, embedded memories, standard peripherals, i/o, controllers and asics. the ST20-GP6 uses the st20 macrocell library to provide the hardware modules required in a gps system. these include: ? dsp hardware ? dual channel uart for serial communications ? two parallel i/o modules providing 16 bits of parallel i/o ? interrupt controller ? real time clock/calendar and watchdog timer ? 128 kbytes of on-chip rom for application code ? 64 kbytes of on-chip ram, of which 16 kbytes is battery backed ? diagnostic control unit and test access port for development support the ST20-GP6 is supported by a range of software and hardware development tools for pc and unix hosts including an ansi-c st20 software toolset and the st20 inquest window based debugging toolkit.
ST20-GP6 7/123 2 ST20-GP6 architecture overview the ST20-GP6 consists of an st20 cpu plus application specifi c dsp hardware for handling gps signals, plus a dual channel uart, rom and ram memory, parallel io, real time clock and watchdog functions. figure 2.1 shows the subsystem modules that comprise the ST20-GP6. these modules are outlined below and more detailed information is given in the following chapters. dsp the ST20-GP6 includes dsp hardware for processing signals from the gps satellites. the dsp module generates the pseudo-random noise (prn) signals, and de-spreads the incoming signal. it consists of a down conversion stage that takes the 4 mhz input signal down to nominally zero frequency both in-phase and quadrature (i & q). this is followed by 12 parallel hardware channels for satellite tracking, whose output is passed to the cpu for further software processing at a programmable interval, nominally every millisecond. cpu the central processing unit (cpu) on the ST20-GP6 is the st20 32-bit processor core. it contains instruction processing logic, instruction and data pointers, and an operand register. it directly accesses the high speed on-chip memory, which can store data or programs. the processor can access up to 4 mbytes of memory via the programmable memory interface.
ST20-GP6 8/123 figure 2.1 ST20-GP6 architectural block diagram memory subsystem the ST20-GP6 on-chip memory system provides 60 mbytes/s internal data bandwidth, supporting pipelined 2-cycle internal memory access at 30 ns cycle times. the ST20-GP6 memory system consists of sram, rom and a programmable external memory interface (emi). gps radio 12 channel gps low controller power real time clock programmable memory interface 128k 64k sram ST20-GP6 st20 cpu interrupt controller serial communications parallel input/output . 2 uart hardware dsp 16 interrupts user position output in ascii . . rom diagnostic control unit test access port system services reset clock
ST20-GP6 9/123 the ST20-GP6 can use 8 or 16-bit external ram, 8 or 16-bit external rom, and has a 20-bit address bus. the ST20-GP6 product has 64 kbytes of on-chip sram. this is in 4 banks of 16 kbytes. one of these banks is powered from the back-up battery supply. the ST20-GP6 has 128 kbytes of rom for application code. the ST20-GP6 memory interface controls the movement of data between the ST20-GP6 and off- chip memory. it is designed to support memory subsystems without any external support logic and is programmable to support a wide range of memory types. memory is divided into 4 banks which can each have different memory characteristics and each bank can access up to 1 mbyte of external memory. the normal memory provision in a simple gps receiver is a single 64k x 16-bit rom or flash rom (70, 90 or 100 ns access time). the internal 64 kbyte ram is suffi cient for application use, however for development purposes external ram may be added. the ST20-GP6 can support up to 1 mbyte of sram plus 1 mbyte of rom, enabling additional functions to be added if required. low power controller, real time clock and watchdog timer the ST20-GP6 has power-down capabilities confi gurable in software. when powered down, a timer can be used as an alarm, re-activating the cpu after a programmed delay. this is suitable for ultra low power or solar powered applications such as container tracking, railway truck tracking, or marine navigation buoys that must check they are on station at intervals. there is also a watchdog timer (wdt), resetting the system if it times out. the watchdog timer function is enabled by an external pin ( wdenable ). the wdt has a counter, clocked to give a nominal 2 second delay. a status fl ag ( notwdreset ) is set by a watchdog reset. this can be used to indicate to application code that the system was reset by the watchdog timer. the real time clock (rtc) provides a set of continuously running counters to provide a clock- calendar function. the counter values can be written to set the current time/data. the rtc is clocked by a 32,768 hz crystal oscillator and has a separate power supply so that it can continue to run when the rest of the chip is powered down. the rtc contains two counters: a 30-bit `milliseconds' counter and a 16-bit `weeks' counter. this allows large time values to be represented to high accuracy. note that the milliseconds counter is actually clocked at 1.024 khz and this must be handled by software. the ST20-GP6 is designed for 0.35 micron, 3.3 v cmos technology and runs at speeds of up to 50 mhz. 3.3 v operation provides reduced power consumption internally and allows the use of low power peripherals. in addition, a power-down mode is available on the ST20-GP6. the different power levels of the ST20-GP6 are listed below. ? o perating power e power consumed during functional operation. ? stand-by power e power consumed during little or no activity. the cpu is idle but ready to immediately respond to an interrupt/reschedule. ? power-down e clocks are stopped and power consumption is signifi cantly reduced. func- tional operation is stalled. normal functional operation can be resumed from previous state as soon as the clocks are stable. no information is lost during power down as all internal logic is static.
ST20-GP6 10/123 ? power to most of the chip removed e only the real time clock supply ( rtcvdd ) power on. in power-down mode the processor and all peripherals are stopped, including the external memory controller and optionally the pll. effectively the internal clock is stopped and functional operation is stalled. on restart the clock is restarted and the chip resumes normal functional operation. serial communications the ST20-GP6 has two uarts (asynchronous serial controllers (ascs)) for serial communication. the uarts provide an asynchronous serial interface and can be programmed to support a range of baud rates and data formats, for example, data size, stop bits and parity. interrupt subsystem the ST20-GP6 interrupt subsystem supports eight prioritized interrupts. four interrupts are connected to on-chip peripherals (2 for the uarts, 2 for the programmable io), two are available as external interrupt pins and two are spare. each interrupt level has a higher priority than the previous and each level supports only one software handler process. note that interrupt handlers must not prevent the gps dsp data traffic from being handled. during continuous operation this has 1 ms latency and is not a problem, but during initial acquisition it has a32 m s rate and thus all interrupts must be disabled except if used to stop gps operation. parallel io module sixteen bits of parallel io are provided. each bit is programmable as an output or an input. edge detection logic is provided which can generate an interrupt on any change of an input bit. jtag test access port the test access port (tap) supports the ieee 1149.1 jtag test standard. diagnostic controller the diagnostic controller is a programmable module which connects directly into the cpu. it can be accessed by the tap. this allows debugging systems to be used which do not affect cpu performance or intrude into application code. debugging support includes: ? hardware breakpoint and watchpoint ? real time trace ? external lsa triggering support it is also used to provide system services, including booting the cpu. system services module the ST20-GP6 system services module includes: ? reset and initialization port. ? phase locked loop (pll) e accepts 16.368 mhz input and generates all the internal high frequency clocks needed for the cpu.
ST20-GP6 11/123 3 digital signal processing module the ST20-GP6 chip includes 12 channel gps correlation dsp hardware. it is designed to handle twelve satellites, two of which can be initialized to support the rtca-sc159 specifi cation. the digital signal processing (dsp) module extracts gps data from the incoming if (intermediate frequency) data. there are a number of stages of processing involved; these are summarized below and in figure 3.1. after the 12 pairs of hardware correlators, the data for all channels are time division multiplexed onto the appropriate internal buses (i.e. values for each channel are passed in sequence, for example: i 1 ,q 1 ,i 2 ,q 2 ... i 12 ,q 12 ,i 1 ,q 1 ). figure 3.1 dsp module block diagram the main stages of processing are as follows: data sampling this stage removes any meta-stability caused by the asynchronous input data coming from an analogue source (the radio receiver). the data at this point consists of a carrier of nominally 4.092 mhz with a bandwidth of approximately 1 mhz. this stage is common to all 12 channels. i correlator (x 12) q correlator (x 12) frequency converter a frequency converter b accumulator st20 cpu accessible data sampler 4 mhz if input generator (x 12) numerically controlled oscillator registers pseudo random noise sequence dma interface
ST20-GP6 12/123 frequency conversion (a) the fi rst frequency converter mixes the sampled if data with the (nominal) 4.092 mhz signal. this is done twice with a quarter cycle offset to produce i and q (in-phase and quadrature) versions of the data at nominal zero centre frequency (this can actually be up to 132 khz due to errors such as doppler shift, crystal accuracy, etc.). the sum frequency (~8 mhz) is removed by low-pass fi lter- ing in the correlator. this stage is common to all 12 channels. correlation against pseudo-random sequence the gps data is transmitted as a spread-spectrum signal (with a bandwidth of about 2 mhz). in order to recover the data it is necessar y to correlate against the same pseudo-random noise (prn) signal that was used to transmit the data. the output of the correlator accumulator is sam- pled at 264 khz. the prn sequences come from the prn generator. there is a correlator for the i and q signals for each of the 12 channels. the output signal is now narrowband. frequency conversion (b) the second stage of frequency conversion mixes the data with the local oscillator signal generated by the numerically controlled oscillator (nco). this signal is locked, under software control, to the space vehicle (sv) frequency and phase to remove the errors and take the frequency and band- width of the data down to 0 and 50 hz respectively. filtering to 500 hz is achieved in hardware, to 50 hz in software. this stage is shared by time division multiplexing between all 12 channels. this is loss-free as the stage supports 12 channels x 264 khz, approximately 3 mhz, well within its 16 mhz clock rate. result integration the fi nal stage sums the i and q values for each channel over a user defi ned period. in normal operation, the sampling period is slightly less than the 1ms length of the prn sequence. this ensures that no data is lost, although it may mean that some data samples are seen twice e this is handled (mainly) in software. the sampling period can also be programmed to be much shorter (i.e. a higher cut-off frequency for the fi lter) when the system is trying to fi nd new satellites (`acquisition mode'). there are two further stages of buffering for the accumulated 16-bit i and q values for each chan- nel. these allow for the slightly different time domains involved 1 . the results after hardware processing of the signal, using the parameters set in the dsp registers, refer to section 3.1, are delivered to the cpu via a dma engine in packet format. the cpu should perform an in (input) instruction on the appropriate channel (see address map, figure 8.1 on page 53) in order to read a packet. the format of the 62-byte packets is given in figure 3.2. these represent a two byte header, fol- lowed by the 16-bit i-values for 12 channels, then the 16-bit q-values for 12 channels, then the 8-bit timestamp values for the 12 channels. the i and q values are sent least signifi cant byte fi rst. the 2 1. data sampled in sv time, data transmitted to the cpu at fi xed intervals.
ST20-GP6 13/123 byte header contains: a `sync' byte with the value #1b, and a `sample rate' byte which contains the two samplerate bits from the dspcontrol register, see table 3.1. packets are delivered at the rate selected by the dspcontrol register, even if new data is not avail- able. in this case, the data value for the fi eld is set to #8000. this guarantees that synchronism is maintained between the satellite one-millisecond epochs and the receiver, despite time-of-recep- tion variations due to the varying path length from the satellite. figure 3.2 dsp packet format 3.1 dsp module registers the gps hardware channels of the ST20-GP6 are controlled by three sets of registers: 1 dspcontrol register 2 prncode0-11 and prnphase0-11 registers 3 ncofrequency0-11 and ncophase0-11 registers the base addresses for the dsp registers are given in the memory map chapter. dspcontrol register the dspcontrol register determines whether the prn generators are on (normal use) or disabled (for built-in-self-test of a system), whether the system is in tracking mode (840/970 m s output rate) or initial acquisition mode (31/62 m s), and selects which of the two rates for each mode. it also 62 byte packet every 840/970/31/62 m s absent 16-bit values padded with #8000 12 x 8-bit time values 12 x 16-bit q values 12 x 16-bit i values 16-bit header sync sample rate acquisition mode first packet (in sv ms) t[7:6] = 10 t[5:0] = time[5:0] remaining packets t[7:6] = 00 t[5:0] = sequence number (sequence numbers are 2 to 16 or 32) tracking mode t[7:6] = 10 t[5:0] = time[5:0]
ST20-GP6 14/123 determines whether the accumulated carrier phase in the nco are reset to zero automatically or continue from their existing value. the bit allocations are given in table 3.1. prncode0-11 registers the prncode0-11 registers choose the code for the particular satellite, and writing these causes a reset to the accumulated carrier phase in the nco for the corresponding channel, if enabled by the dspcontrol register. the bit-fi elds for selecting particular gps satellites are given in table 3.3. dspcontrol dsp base address + #140 write only bit bit field function 1:0 samplerate these bits control the sampling rate (the rate at which data is sent to the dma controller). the encoding of these bits is as follows: samplerate[1:0] transfer period no. of samples accumulated mode 00 840 m s 256 tracking 01 970 m s 256 10 31 m s 8 acquisition 11 62 m s16 2 ncoresetenable when set to 1, the accumulated nco phase for a channel is reset when the cor- responding prn code register is written. 3 prndisable when set to 1, all prn generators are disabled. table 3.1 dspcontrol register format prncode0-11 dsp base address + #00 to #2c write only bit bit field function 6:0 prncode satellite code as a 7-bit value. table 3.2 prncode0-11 register format
ST20-GP6 15/123 for channels 0 and 1, rtca-sc159 satellite codes can also be selected. this is achieved by set- ting the prncode0-11 register appropriately and also writing the initial value for the satellite to the satellite id prncode0-11 register value taps selected from g2 shift register a by bits 6 to 4 by bits 3 to 0 1 #62 6 2 2 #73 7 3 3 #04 8 4 4 #15 9 5 5 #11 9 1 6 #22 10 2 7 #01 8 1 8 #12 9 2 9 #23 10 3 10 #32 3 2 11 #43 4 3 12 #65 6 5 13 #76 7 6 14 #07 8 7 15 #18 9 8 16 #29 10 9 17 #41 4 1 18 #52 5 2 19 #63 6 3 20 #74 7 4 21 #05 8 5 22 #16 9 6 23 #31 3 1 24 #64 6 4 25 #75 7 5 26 #06 8 6 27 #17 9 7 28 #28 10 8 29 #61 6 1 30 #72 7 2 31 #03 8 3 32 #14 9 4 - #25 10 5 - #24 10 4 - #71 7 1 - #02 8 2 - #24 10 4 waas b #20 10 0 table 3.3 prncode0-11 register value a. refer to the us dod document icd-gps-200. b. it is the responsibility of the software to ensure that when this value is selected, a suitable value has been written into the prninitialval0-1 register. if this channel is later used for a standard gps satellite, the prninitialval0-1 must be set to all ones (#3ff).
ST20-GP6 16/123 prninitialval0-1 register, see table 3.8. if uninitialized by the software, the prninitialval register defaults to 11 1111 1111 (#3ff) as required for gps satellites. the prncode0-11 and prninitialval0-1 registers are normally written only when the satellite is fi rst chosen. prnphase0-11 registers the prn0-11phase registers determine the relative delay between the receiver master clock, and the start of the one millisecond repetitive code sequence. the code sequence starts when the receiver clock counter (invisible to the software except through message timestamps) reaches the value written to the prnphase0-11 register. the prnphase0-11 register must only be written once per satellite milliseconds-epoch, which varies from the receiver epoch dynamically due to sat- ellite motion. synchronism with the software is achieved by reading the register, when a write enable fl ag is returned. if not enabled, the write operation is abandoned by the software. the 19-bit value comprises three fi elds. the 3 least signifi cant bits represent the fractional-delay in eighths of a code-chip. the middle 10 bits represent the integer delay in code-chips, 0-1022, with the value 1023 illegal. the upper 6 most signifi cant bits represent the delay in integer milliseconds. note also that the eighth-chip resolution of the code generator is not suffi cient for positioning. at 125 ns it represents approximately 40 m of range, over 100 m of position. the software must main- tain the range measurements around the 1 ns resolution level in a 32-bit fi eld, and send an appro- priate 19-bit sub-field to the register. note, care must be taken when calculating this fi eld from a computed delay, or vice versa, to allow for the missing value 1023. the overall register bit-fi eld can- not be used mathematically as a single binary number. prnphase0-11wren registers the prnphase0-11wren fl ags are active low fl ags that record when the prnphase0-11 register can be updated. the prnphasewren fl ag for a channel is set high when the corresponding prn- phase register is written. the fl ag is reset again when the value written is loaded into the prn gen- prnphase0-11 dsp base address + #40 to #6c write only bit bit field function 2:0 fractionaldelay fractional delay in eighths of a code-chip. 12:3 integerdelay integer delay in code-chips. value 0-1022. note, the value 1023 is illegal. 18:13 delay delay in integer milliseconds. table 3.4 prnphase0-11 register format
ST20-GP6 17/123 erator. note, the prnphase0-11 register should only be updated when the prnphase0-11wren register has been cleared by the hardware. ncofrequency0-11 registers the ncofrequency0-11 registers hold a signed 18-bit value that is added repetitively, ignoring overflows, to the accumulated nco phase from which the nco sine and cosine waveforms are generated. the addition is performed at a 264 khz rate (16.368mhz/62). the accumulated nco phase is not accessible to the software, but can be cleared when initialising the channel if enabled by the dspcontrol register. each unit value in the ncofrequency0-11 register represents 264khz/(2 18 ), i.e. 1.007080078125 hz. if the extreme values are written, #1ffff and #20000, the sine wave generated will be at approxi- mately +132 khz, and precisely -132 khz respectively. ncophase0-11 registers the ncophase0-11 registers contents are added to the accumulated phase to correct the carrier for the fi nal 1 hz that cannot be resolved by the nco frequency. this addition is not cumulative, and the value must be updated regularly by the software as a result of carrier phase errors mea- sured on the satellite signal. the register holds a signed 7-bit fi eld representing +/-180 degrees total in steps of 2.8125 degrees (360/128). prnphase0-11wren dsp base address + #40 to #6c read only bit bit field function 0 prnphasewren set when the corresponding prnphase0-11 register is set. table 3.5 prnphase0-11wren register format ncofrequency0-11 dsp base address + #80 to #ac write only bit bit field function 17:0 ncofrequency nco frequency as a signed 18-bit value. table 3.6 ncofrequency0-11 register format ncophase0-11 dsp base address + #c4 to #ec write only bit bit field function 6:0 ncophase nco phase as a signed 7-bit value representing +/-180 degrees total in steps of 2.8125 degrees (360/128). table 3.7 ncophase0-11 register format
ST20-GP6 18/123 prninitialval0-1 registers the initial value for the two rtca-sc159 capable satellites channels should be written to the prninitialval0-1 registers. the value can be found in the rtca-sc159 specifi cation . note : the value written to the register is the initial value defi ned by rtca-sc159 for the prn required. the conversion from `big-endian' as used in the specifi cation to `little-endian' as conven- tionally used in st20 architectures has been implemented in the hardware. if uninitialized by the software, this register defaults to 11 1111 1111 (#3ff) as required for gps satellites. prninitialval0-1 dsp base address + #100, #104 write only bit bit field function 9:0 initialvalue initial value of the rtca-sc159 satellite channel. table 3.8 prninitialval0-1 register format
ST20-GP6 19/123 4 central processing unit the central processing unit (cpu) is the st20 32-bit processor core. it contains instruction pro- cessing logic, instruction and data pointers, and an operand register. it can directly access the high speed on-chip memory, which can store data or programs. where larger amounts of memory are required, the processor can access memory via the external memory interface (emi). the processor provides high performance: ? fast integer multiply - 4 cycle multiply ? fast bit shift - single cycle barrel shifter ? byte and part-word handling ? scheduling and interrupt support ? 64-bit integer arithmetic support. the scheduler provides a single level of pre-emption. in addition, multi-level pre-emption is pro- vided by the interrupt subsystem, see chapter 5 for details. additionally, there is a per-priority trap handler to improve the support for arithmetic errors and illegal instructions, refer to section 4.6. 4.1 registers the cpu contains six registers which are used in the execution of a sequential integer process. the six registers are: ? the workspace pointer ( wptr ) which points to an area of store where local data is kept. ? the instruction pointer ( iptr ) which points to the next instruction to be executed. ? the status register ( status ). ? the areg , breg and creg registers which form an evaluation stack. the areg , breg and creg registers are the sources and destinations for most arithmetic and logi- cal operations. loading a value into the stack pushes breg into creg , and areg into breg , before loading areg . storing a value from areg , pops breg into areg and creg into breg . creg is left undefi ned. figure 4.1 registers used in sequential integer processes areg breg creg wptr iptr local data program registers
ST20-GP6 20/123 expressions are evaluated on the evaluation stack, and instructions refer to the stack implicitly. for example, the add instruction adds the top two values in the stack and places the result on the top of the stack. the use of a stack removes the need for instructions to explicitly specify the location of their operands. no hardware mechanism is provided to detect that more than three values have been loaded onto the stack; it is easy for the compiler to ensure that this never happens. note that a location in memory can be accessed relative to the workspace pointer, enabling the workspace to be of any size. the use of shadow registers provides fast, simple and clean context switching. 4.2 processes and concurrency the following section describes `default' behavior of the cpu and it should be noted that the user can alter this behavior, for example, by disabling timeslicing, installing a user scheduler, etc. a process starts, performs a number of actions, and then either stops without completing or termi- nates complete. typically, a process is a sequence of instructions. the cpu can run several pro- cesses in parallel (concurrently). processes may be assigned either high or low priority, and there may be any number of each. the processor has a microcoded scheduler which enables any number of concurrent processes to be executed together, sharing the processor time. this removes the need for a software kernel, although kernels can still be written if desired. at any time, a process may be active - being executed, - interrupted by a higher priority process, - on a list waiting to be executed. inactive - waiting to input, - waiting to output, - waiting until a specified time. the scheduler operates in such a way that inactive processes do not consume any processor time. each active high priority process executes until it becomes inactive. the scheduler allocates a por- tion of the processor's time to each active low priority process in turn (see section 4.3). active pro- cesses waiting to be executed are held in two linked lists of process work spaces, one of high priority processes and one of low priority processes. each list is implemented using two registers, one of which points to the fi rst process in the list, the other to the last. in the linked process list shown in figure 4.2, process s is executing and p , q and r are active, awaiting execution. only the low priority process queue registers are shown; the high priority process ones behave in a similar manner.
ST20-GP6 21/123 figure 4.2 linked process list each process runs until it has completed its action or is descheduled. in order for several pro- cesses to operate in parallel, a low priority process is only permitted to execute for a maximum of two timeslice periods. after this, the machine deschedules the current process at the next timeslic- ing point, adds it to the end of the low priority scheduling list and instead executes the next active process. the timeslice period is 1ms. there are only certain instructions at which a process may be descheduled. these are known as descheduling points. a process may only be timesliced at certain descheduling points. these are known as timeslicing points and are defi ned in such a way that the operand stack is always empty. this removes the need for saving the operand stack when timeslicing. as a result, an expression evaluation can be guaranteed to execute without the process being timesliced part way through. whenever a process is unable to proceed, its instruction pointer is saved in the process workspace and the next process taken from the list. the processor core provides a number of special instructions to support the process model, includ- ing startp (start process) and endp (end process). when a main process executes a parallel con- struct, startp is used to create the necessar y additional concurrent processes. a startp instruction creates a new process by adding a new workspace to the end of the scheduling list, enabling the new concurrent process to be executed together with the ones already being executed. when a process is made active it is always added to the end of the list, and thus cannot pre-empt pro- cesses already on the same list. the correct termination of a parallel construct is assured by use of the endp instruction. this uses a data structure that includes a counter of the parallel construct components which have still to ter- function high priority low priority pointer to front of active process list fptrreg0 fptrreg1 pointer to back of active process list bptrreg0 bptrreg1 table 4.1 priority queue control registers p q r s areg breg creg wptr iptr fptrreg1 bptrreg1 registers local data iptr.s link.s iptr.s link.s iptr.s program
ST20-GP6 22/123 minate. the counter is initialized to the number of components before the processes are started. each component ends with an endp instruction which decrements and tests the counter. for all but the last component, the counter is non zero and the component is descheduled. for the last com- ponent, the counter is zero and the main process continues. 4.3 priority the following section describes `default' behavior of the cpu and it should be noted that the user can alter this behavior, for example, by disabling timeslicing and priority interrupts. the processor can execute processes at one of two priority levels, one level for urgent (high prior- ity) processes, one for less urgent (low priority) processes. a high priority process will always exe- cute in preference to a low priority process if both are able to do so. high priority processes are expected to execute for a short time. if one or more high priority pro- cesses are active, then the fi rst on the queue is selected and executes until it has to wait for a com- munication, a timer input, or until it completes processing. if no process at high priority is active, but one or more processes at low priority are active, then one is selected. low priority processes are periodically timesliced to provide an even distribution of pro- cessor time between tasks which use a lot of computation. if there are n low priority processes, then the maximum latency from the time at which a low priority process becomes active to the time when it starts processing is the order of 2 n timeslice periods. it is then able to execute for between one and two timeslice periods, less any time taken by high pri- ority processes. this assumes that no process monopolizes the time of the cpu; i.e. it has fre- quent timeslicing points. the specifi c condition for a high priority process to start execution is that the cpu is idle or running at low priority and the high priority queue is non-empty. if a high priority process becomes able to run while a low priority process is executing, the low pri- ority process is temporarily stopped and the high priority process is executed. the state of the low priority process is saved into `shadow' registers and the high priority process is executed. when no further high priority processes are able to run, the state of the interrupted low priority process is re- loaded from the shadow registers and the interrupted low priority process continues executing. instructions are provided on the processor core to allow a high priority process to store the shadow registers to memory and to load them from memory. instructions are also provided to allow a pro- cess to exchange an alternative process queue for either priority process queue (see table 7.21 on page 49). these instructions allow extensions to be made to the scheduler for custom run-time ker- nels. a low priority process may be interrupted after it has completed execution of any instruction. in addition, to minimize the time taken for an interrupting high priority process to start executing, the potentially time consuming instructions are interruptible. also some instructions may be aborted, and are restarted when the process next becomes active (refer to the instruction set chapter).
ST20-GP6 23/123 4.4 process communications communication between processes takes place over channels, and is implemented in hardware. communication is point-to-point, synchronized and unbuffered. as a result, a channel needs no process queue, no message queue and no message buffer. a channel between two processes executing on the same cpu is implemented by a single word in memory; a channel between processes executing on different processors is implemented by point- to-point links. the processor provides a number of operations to support message passing, the most important being in (input message) and out (output message). the in and out instructions use the address of the channel to determine whether the channel is internal or external. this means that the same instruction sequence can be used for both hard and soft channels, allowing a process to be written and compiled without knowledge of where its chan- nels are implemented. communication takes place when both the inputting and outputting processes are ready. conse- quently, the process which fi rst becomes ready must wait until the second one is also ready. the inputting and outputting processes only become active when the communication has completed. a process performs an input or output by loading the evaluation stack with, a pointer to a message, the address of a channel, and a count of the number of bytes to be transferred, and then executing an in or out instruction. 4.5 timers there are two 32-bit hardware timer clocks which `tick' periodically. these are independent of any on-chip peripheral real time clock. the timers provide accurate process timing, allowing processes to deschedule themselves until a specifi c time. one timer is accessible only to high priority processes and is incremented approximately every microsecond, cycling completely in approximately 4295 seconds. the other is accessible only to low priority processes and is incremented approximately every 64 microseconds, giving 15625 ticks per second. it has a full period of approximately 76 hours. timer frequencies are approximate. the current value of the processor clock can be read by executing a ldtimer (load timer) instruction. a process can arrange to perform a tin (timer input), in which case it will become ready to execute after a specifi ed time has been reached. the tin instruction requires a time to be specifi ed. if this time is in the `past' then the instruction has no effect. if the time is in the `future' then the process is descheduled. when the specifi ed time is reached the process becomes active. in addition, the register function clockreg0 current value of high priority (level 0) process clock. clockreg1 current value of low priority (level 1) process clock. tnextreg0 indicates time of earliest event on high priority (level 0) timer queue. tnextreg1 indicates time of earliest event on low priority (level 1) timer queue. tptrreg0 high priority timer queue. tptrreg1 low priority timer queue. table 4.2 timer registers
ST20-GP6 24/123 ldclock (load clock), stclock (store clock) instructions allow total control over the clock value and the clockenb (clock enable), clockdis (clock disable) instructions allow each clock to be individually stopped and re-started. figure 4.3 shows two processes waiting on the timer queue, one waiting for time 21, the other for time 31. figure 4.3 timer registers 4.6 traps and exceptions a software error, such as arithmetic overflow or array bounds violation, can cause an error fl ag to be set in the cpu. the fl ag is directly connected to the errorout pin. both the fl ag and the pin can be ignored, or the cpu stopped. stopping the cpu on an error means that the error cannot cause further corruption. as well as containing the error in this way it is possible to determine the state of the cpu and its memory at the time the error occurred. this is particularly useful for postmortem debugging where the debugger can be used to examine the state and history of the processor leading up to and causing the error condition. in addition, if a trap handler process is installed, a variety of traps/exceptions can be trapped and handled by software. a user supplied trap handler routine can be provided for each high/low pro- cess priority level. the handler is started when a trap occurs and is given the reason for the trap. the trap handler is not re-entrant and must not cause a trap itself within the same group. all traps can be individually masked. 4.6.1 trap groups the trap mechanism is arranged on a per priority basis. for each priority there is a handler for each group of traps, as shown in figure 4.4. clockreg0 tnextreg0 tptrreg0 work spaces program 5 21 31 empty comparator alarm 21
ST20-GP6 25/123 figure 4.4 trap arrangement there are four groups of traps, as detailed below. ? breakpoint this group consists of the breakpoint trap. the breakpoint instruction ( j0 ) calls the break- point routine via the trap mechanism. ? errors the traps in this group are integererror and overflow . overflow represents arithmetic over- fl ow, such as arithmetic results which do not fi t in the result word. integererror represents errors caused when data is erroneous, for example when a range checking instruction fi nds that data is out of range. ? system operations this group consists of the loadtrap , storetrap and illegalopcode traps. the illegalopcode trap is signalled when an attempt is made to execute an illegal instruction. the loadtrap and storetrap traps allow a kernel to intercept attempts by a monitored process to change or examine trap handlers or trapped process information. it enables a user program to sig- nal to a kernel that it wishes to install a new trap handler. ? scheduler the scheduler trap group consists of the externalchannel, internalchannel, timer, timeslice, run, signal, processinterrupt and queueempty traps. the processinterrupt trap signals that the machine has performed a priority interrupt from low to high. the queueempty trap indicates that there is no further executable work to perform. the other traps in this group indicate that the hardware scheduler wants to schedule a process on a process queue, with the different traps enabling the different sources of this to be moni- tored. the scheduler traps enable a software scheduler kernel to use the hardware scheduler to implement a multi-priority software scheduler. note that scheduler traps are different from other traps as they are caused by the micro- scheduler rather than by an executing process. trap groups encoding is shown in table 4.3 below. these codes are used to identify trap groups to various instructions. low priority traps high priority traps cpu error trap handler system operations trap handler scheduler trap handler breakpoint trap handler cpu error trap handler system operations trap handler scheduler trap handler breakpoint trap handler
ST20-GP6 26/123 in addition to the trap groups mentioned above, the causeerror fl ag in the status register is used to signal when a trap condition has been activated by the causeerror instruction. it can be used to indicate when trap conditions have occurred due to the user setting them, rather than by the sys- tem. 4.6.2 events that can cause traps table 4.4 summarizes the events that can cause traps and gives the encoding of bits in the trap status and enable words. trap group code breakpoint 0 cpu errors 1 system operations 2 scheduler 3 table 4.3 trap group codes trap cause status/enable codes trap group comments breakpoint 00 when a process executes the breakpoint instruction ( j0 ) then it traps to its trap handler. integererror 1 1 integer error other than integer overflow - e.g. explicitly checked or explicitly set error. overflow 21 integer overfl ow or integer division by zero. illegalopcode 3 2 attempt to execute an illegal instruction. this is signalled when opr is executed with an invalid operand. loadtrap 42 when the trap descriptor is read with the ldtraph instruction or when the trapped process status is read with the ldtrapped instruction. storetrap 52 when the trap descriptor is written with the sttraph instruction or when the trapped process status is written with the sttrapped instruction. internalchannel 63 scheduler trap from internal channel. externalchannel 7 3 scheduler trap from external channel. timer 83 scheduler trap from timer alarm. timeslice 93 scheduler trap from timeslice. run 10 3 scheduler trap from runp (run process) or startp (start process). signal 11 3 scheduler trap from signal . processinterrupt 12 3 start executing a process at a new priority level. queueempty 13 3 caused by no process active at a priority level. causeerror 15 (status only) any, encoded 0-3 signals that the causeerror instruction set the trap fl ag. table 4.4 trap causes and status / enable codes
ST20-GP6 27/123 4.6.3 trap handlers for each trap handler there is a trap handler structure and a trapped process structure. both the trap handler structure and the trapped process structure are in memory and can be accessed via instructions, see section 4.6.4. the trap handler structure specifi es what should happen when a trap condition is present, see table 4.5. the trapped process structure saves some of the state of the process that was running when the trap was taken, see table 4.6. in addition, for each priority, there is an enables register and a status register. the enables regis- ter contains fl ags to enable each cause of trap. the status register contains fl ags to indicate which trap conditions have been detected. the enables and status register bit encodings are given in table 4.4. a trap will be taken at an interruptible point if a trap is set and the corresponding trap enable bit is set in the enables register. if the trap is not enabled then nothing is done with the trap condition. if the trap is enabled then the corresponding bit is set in the status register to indicate the trap con- dition has occurred. when a process takes a trap the processor saves the existing iptr , wptr , status and enables in the trapped process structure. it then loads iptr , wptr and status from the equivalent trap handler structure and ands the value in enables with the value in the structure. this allows the user to dis- able various events while in the handler, in particular a trap handler must disable all the traps of its trap group to avoid the possibility of a handler trapping to itself. the trap handler then executes. the values in the trapped process structure can be examined using the ldtrapped instruction (see section 4.6.4). when the trap handler has completed its opera- comments location iptr iptr of trap handler process. base + 3 wptr wptr of trap handler process. a null wptr indicates that a trap handler has not been installed. base + 2 status contains the status register that the trap handler starts with. base + 1 enables a word which encodes the trap enable and global interrupt masks, which will be anded with the existing masks to allow the trap handler to disable various events while it runs. base + 0 table 4.5 trap handler structure comments location iptr points to the instruction after the one that caused the trap condition. base + 3 wptr wptr of the process that was running when the trap was taken. base + 2 status the relevant trap bit is set, see table 4.3 for trap codes. base + 1 enables interrupt enables. base + 0 table 4.6 trapped process structure
ST20-GP6 28/123 tion it returns to the trapped process via the tret (trap return) instruction. this reloads the values saved in the trapped process structure and clears the trap fl ag in status . note that when a trap handler is started, areg , breg and creg are not saved. the trap handler must save the areg , breg , creg registers using stl (store local). 4.6.4 trap instructions trap handlers and trapped processes can be set up and examined via the ldtraph , sttraph , ldtrapped and sttrapped instructions. table 4.7 describes the instructions that may be used when dealing with traps. the fi rst four instructions transfer data to/from the trap handler structures or trapped process struc- tures from/to an area in memory. in these instructions areg contains the trap group code (see table 4.3) and breg points to the 4 word area of memory used as the source or destination of the transfer. in addition creg contains the priority of the handler to be installed/examined in the case of ldtraph or sttraph. ldtrapped and sttrapped apply only to the current priority. if the loadtrap trap is enabled then ldtraph and ldtrapped do not perform the transfer but set the loadtrap trap fl ag. if the storetrap trap is enabled then sttraph and sttrapped do not perform the transfer but set the storetrap trap fl ag. the trap enable masks are encoded by an array of bits (see table 4.4) which are set to indicate which traps are enabled. this array of bits is stored in the lower half-word of the enables register. there is an enables register for each priority. traps are enabled or disabled by loading a mask into areg with bits set to indicate which traps are to be affected and the priority to affect in breg . exe- cuting trapenb ors the mask supplied in areg with the trap enables mask in the enables register for the priority in breg . executing trapdis negates the mask supplied in areg and ands it with the trap enables mask in the enables register for the priority in breg . both instructions return the pre- vious value of the trap enables mask in areg . instruction meaning use ldtraph load trap handler load the trap handler from memory to the trap handler descriptor. sttraph store trap handler store an existing trap handler descriptor to memory. ldtrapped load trapped load replacement trapped process status from memory. sttrapped store trapped store trapped process status to memory. trapenb trap enable enable traps. trapdis trap disable disable traps. tret trap return used to return from a trap handler. causeerror cause error program can simulate the occurrence of an error. table 4.7 instructions which may be used when dealing with traps
ST20-GP6 29/123 4.6.5 restrictions on trap handlers there are various restrictions that must be placed on trap handlers to ensure that they work cor- rectly. 1 trap handlers must not deschedule or timeslice. trap handlers alter the enables masks, therefore they must not allow other processes to execute until they have completed. 2 trap handlers must have their enable masks set to mask all traps in their trap group to avoid the possibility of a trap handler trapping to itself. 3 trap handlers must terminate via the tret (trap return) instruction . the only exception to this is that a scheduler kernel may use restart to return to a previously shadowed process.
ST20-GP6 30/123 5 interrupt controller the ST20-GP6 supports external interrupts, enabling an on-chip subsystem or external interrupt pin to interrupt the currently running process in order to run an interrupt handling process the ST20-GP6 interrupt subsystem supports eight prioritized interrupts. this allows nested pre- emptive interrupts for real-time system design. in addition, there is an interrupt level controller (refer to chapter 6) which multiplexes incoming interrupts onto the eight programmable interrupt levels. this multiplexing is controllable by software. there are 6 sources of interrupts. four of these are internal (2 for the uarts, 2 for the programmable io) and two are external. all interrupts are a higher priority than the low priority process queue. each interrupt can be pro- grammed to be at a lower priority or a higher priority than the high priority process queue, this is determined by the priority bit in the handlerwptr0-7 registers, see table 5.1 on page 33. note: interrupts ( interrupt0-7 ) which are specifi ed as higher priority must be contiguous from the highest numbered interrupt downwards, i.e. if 4 interrupts are programmed as higher priority and 4 as lower priority the higher priority interrupts must be interrupt7:4 and the lower priority interrupts interrupt3:0 . note that interrupt handlers must not prevent the gps dsp data traffic from being handled. during continuous operation this has 1 ms latency and is not a problem, but during initial acquisition it has a32 m s rate and thus care must be taken with interrupt priorities unless used to stop gps opera- tion. figure 5.1 interrupt priority interrupt 7 interrupt 0 high priority low priority increasing pre-emption . .. . process process interrupt 7 interrupt 0 . .. . when priority bit set to 1 when priority bit set to 1 when priority bit set to 0 when priority bit set to 0
ST20-GP6 31/123 interrupts on the ST20-GP6 are implemented via an on-chip interrupt controller peripheral. an interrupt can be signalled to the controller by one of the following: ? a signal on an external interrupt pin ? a signal from an internal peripheral or subsystem ? software asserting an interrupt in the pending register 5.1 interrupt vector table the interrupt controller contains a table of pointers to interrupt handlers. each interrupt handler is represented by its workspace pointer ( wptr ). the table contains a workspace pointer for each level of interrupt. the wptr gives access to the code, data and interrupt save space of the interrupt handler. the position of the wptr in the interrupt table implies the priority of the interrupt. run-time library support is provided for setting and programming the vector table. 5.2 interrupt handlers at any interruptible point in its execution the cpu can receive an interrupt request from the inter- rupt controller. the cpu immediately acknowledges the request. in response to receiving an interrupt the cpu performs a procedure call to the process in the vec- tor table. the state of the interrupted process is stored in the workspace of the interrupt handler as shown in figure 5.2. each interrupt level has its own workspace. figure 5.2 state of interrupted process before interrupt wptr areg breg creg interrupting high priority wptr wptr iptr status wptr null status process interrupting low priority process or cpu idle handler iptr handler status handler iptr handler status handler iptr handler status
ST20-GP6 32/123 the interrupt routine is initialized with space below wptr . the iptr and status word for the routine are stored there permanently. this should be programmed before the wptr is written into the vector table. the behavior of the interrupt differs depending on the priority of the cpu when the interrupt occurs. when an interrupt occurs when the cpu was running at high priority, and the interrupt is set at a higher priority than the high priority process queue, the cpu saves the current process state ( areg , breg , creg , wptr , iptr and status ) into the workspace of the interrupt handler. the value handlerwptr , which is stored in the interrupt controller, points to the top of this workspace. the values of iptr and status to be used by the interrupt handler are loaded from this workspace and starts executing the handler. the value of wptr is then set to the bottom of this save area. when an interrupt occurs when the cpu was running at high priority, and the interrupt is set at a lower priority than the high priority process queue, no action is taken and the interrupt waits in a queue until all higher priority interrupts have been serviced (see section 5.4). interrupts always take priority over low priority processes. when an interrupt occurs when the cpu was idle or running at low priority, the status is saved. this indicates that no valid process is run- ning ( null status ). the interrupted processes (low priority process) state is stored in shadow regis- ters. this state can be accessed via the ldshadow (load shadow registers) and stshadow (store shadow registers) instructions. the interrupt handler is then run at high priority. when the interrupt routine has completed it must adjust wptr to the value at the start of the han- dler code and then execute the iret (interrupt return) instruction. this restores the interrupted state from the interrupt handler structure and signals to the interrupt controller that the interrupt has completed. the processor will then continue from where it was before being interrupted. 5.3 interrupt latency the interrupt latency is dependent on the data being accessed and the position of the interrupt handler and the interrupted process. this allows systems to be designed with the best trade-off use of fast internal memory and interrupt latency. 5.4 preemption and interrupt priority each interrupt channel has an implied priority fi xed by its place in the interrupt vector table. all interrupts will cause scheduled processes of lower priority to be suspended and the interrupt han- dler started. once an interrupt has been sent from the controller to the cpu the controller keeps a record of the current executing interrupt priority. this is only cleared when the interrupt handler executes a return from interrupt ( iret ) instruction. interrupts of a lower priority arriving will be blocked by the interrupt controller until the interrupt priority has descended to such a level that the routine will execute. an interrupt of a higher priority than the currently executing handler will be passed to the cpu and cause the current handler to be suspended until the higher priority interrupt is serviced. in this way interrupts can be nested and a higher priority interrupt will always pre-empt a lower pri- ority one. deep nesting and placing frequent interrupts at high priority can result in a system where low priority interrupts are never serviced or the controller and cpu time are consumed in nesting interrupt priorities and not executing the interrupt handlers.
ST20-GP6 33/123 5.5 restrictions on interrupt handlers there are various restrictions that must be placed on interrupt handlers to ensure that they interact correctly with the rest of the process model implemented in the cpu. 1 interrupt handlers must not deschedule. 2 interrupt handlers must not execute communication instructions. however they may com- municate with other processes through shared variables using the semaphore signal to synchronize. 3 interrupt handlers must not perform 2d block move instructions. 4 interrupt handlers must not cause program traps. however they may be trapped by a scheduler trap. 5.6 interrupt configuration register s the interrupt controller is allocated a 4k block of memory in the internal peripheral address space. information on interrupts is stored in registers as detailed in the following section. the registers can be examined and set by the devlw (device load word) and devsw (device store word) instructions. note, they can not be accessed using memory instructions. handlerwptr register the handlerwptr registers (1 per interrupt) contain a pointer to the workspace of the interrupt han- dler. it also contains the priority bit which determines whether the interrupt is at a higher or lower priority than the high priority process queue. note, before the interrupt is enabled, by writing a 1 in the mask register, the user (or toolset) must ensure that there is a valid wptr in the register. handlerwptr interrupt controller base address + #00 to #1c read/write bit bit field function 0 priority sets the priority of the interrupt. if this bit is set to 0, the interrupt is a higher priority than the high priority process queue, if this bit is 1, the interrupt is a lower priority than the high priority process queue. 0 high priority 1 low priority 31:2 handlerwptr pointer to the workspace of the interrupt handler. 1 reserved, write 0. table 5.1 handlerwptr register format - one register per interrupt
ST20-GP6 34/123 triggermode register each interrupt channel can be programmed to trigger on rising/falling edges or high/low levels on the external interrupt . note, level triggering is different to edge triggering in that if the input is held at the triggering level, a continuous stream of interrupts is generated. mask register an interrupt mask register is provided in the interrupt controller to selectively enable or disable external interrupts. this mask register also includes a global interrupt disable bit to disable all external interrupts whatever the state of the individual interrupt mask bits. to complement this the interrupt controller also includes an interrupt pending register which con- tains a pending fl ag for each interrupt channel. the mask register performs a masking function on the pending register to give control over what is allowed to interrupt the cpu while retaining the ability to continually monitor external interrupts. on start-up, the mask register is initialized to zeros, thus all interrupts are disabled, both globally and individually. when a 1 is written to the globalenable bit, the individual interrupt bits are still disabled and must also have a 1 individually written to the interruptenable bit to enable the respective interrupt. the mask register is mapped onto two additional addresses so that bits can be set or cleared indi- vidually. triggermode interrupt controller base address + #40 to #5c read/write bit bit field function 2:0 trigger control the triggering condition of the interrupt , as follows: trigger2:0 interrupt triggers on 000 no trigger mode 001 high level - triggered while input high 010 low level - triggered while input low 011 rising edge - low to high transition 100 falling edge - high to low transition 101 any edge - triggered on rising and falling edges 110 no trigger mode 111 no trigger mode table 5.2 triggermode register format - one register per interrupt mask interrupt controller base address + #c0 read/write bit bit field function 7:0 interrupt7:0enable when set to 1, interrupt is enabled. when 0, interrupt is disabled. 16 globalenable when set to 1, the setting of the interrupt is determined by the specifi c interruptenable bit. when 0, all interrupts are disabled. 15:8 reserved, write 0. table 5.3 mask register format
ST20-GP6 35/123 set_mask (address `interrupt base address + #c4') allows bits to be set individually. writing a `1' in this register sets the corresponding bit in the mask register, a `0' leaves the bit unchanged. clear_mask (address `interrupt base address + #c8') allows bits to be cleared individually. writing a `1' in this register resets the corresponding bit in the mask register, a `0' leaves the bit unchanged. pending register the pending register contains a bit per interrupt with each bit controlled by the corresponding interrupt. a read can be used to examine the state of the interrupt controller while a write can be used to explicitly trigger an interrupt. a bit is set when the triggering condition for an interrupt is met. all bits are independent so that sev- eral bits can be set in the same cycle. once a bit is set, a further triggering condition will have no effect. the triggering condition is independent of the mask register. the highest priority interrupt bit is reset once the interrupt controller has made an interrupt request to the cpu. the interrupt controller receives external interrupt requests and makes an interrupt request to the cpu when it has a pending interrupt request of higher priority than the currently executing interrupt handler. the pending register is mapped onto two additional addresses so that bits can be set or cleared individually. set_pending (address `interrupt base address + #84') allows bits to be set individually. writing a `1' in this register sets the corresponding bit in the pending register, a `0' leaves the bit unchanged. clear_pending (address `interrupt base address + #88') allows bits to be cleared individually. writ- ing a `1' in this register resets the corresponding bit in the pending register, a `0' leaves the bit unchanged. note, if the cpu wants to write or clear some bits of the pending register, the interrupts should be masked (by writing or clearing the mask register) before writing or clearing the pending register. the interrupts can then be unmasked. exec register the exec register keeps track of the currently executing and pre-empted interrupts. a bit is set when the cpu starts running code for that interrupt. the highest priority interrupt bit is reset once the interrupt handler executes a return from interrupt ( iret ). pending interrupt controller base address + #80 read/write bit bit field function 7:0 pendingint7:0 interrupt pending bit. table 5.4 bit fi elds in the pending register exec interrupt controller base address + #100 read/write bit bit field function 7:0 interrupt7:0exec set to 1 when the cpu starts running code for interrupt. table 5.5 bit fi elds in the exec register
ST20-GP6 36/123 the exec register is mapped onto two additional addresses so that bits can be set or cleared indi- vidually. set_exec (address `interrupt base address + #104') allows bits to be set individually. writing a `1' in this register sets the corresponding bit in the exec register, a `0' leaves the bit unchanged. clear_exec (address `interrupt base address + #108') allows bits to be cleared individually. writing a `1' in this register resets the corresponding bit in the exec register, a `0' leaves the bit unchanged.
ST20-GP6 37/123 6 interrupt level controller there are 6 interrupts (of which 2 are external) generated in the ST20-GP6 system and each of these is assigned to one of the interrupt controller's 8 inputs. thus each of the interrupt controller's inputs responds to zero or more of the 8 system interrupts. an interrupt handler routine is able to ascertain the source of an interrupt where two or more sys- tem interrupts are assigned to one handler by doing a device read from the inputinterrupts regis- ter (see table 6.3) and examining the bits that correspond to the system interrupts assigned to that handler. the interrupt level controller has additional functionality to support the low power controller. the external interrupts are monitored and a signal is generated for the low power controller which tells it when any of them goes to a pre-determined level. this level is programmable for each external interrupt, and in addition each interrupt can be selectively masked. 6.1 interrupt assignments the interrupts from the peripherals on the ST20-GP6 are assigned as follows: these interrupts are inputs to the interrupt level controller. this allows these interrupts to be assigned to any of eight interrupt priority levels and for multiple interrupts to share a priority level. 6.2 interrupt level controller registers the interrupt level controller is programmable via confi guration registers. these registers can be examined and set by the devlw (device load word) and devsw (device store word) instructions. intpriority registers the priority assigned to each of the input interrupts is programmable via the intpriority registers. the interrupt level controller asserts interrupt output n when one or more of the input interrupts with programmed priority equal to n are high. it is level sensitive and re-timed at the input, thus incurring one cycle of latency. interrupt peripheral signals ored together to generate interrupt signal 0 pio a compare function 1 pio b compare function 2 asc0 asc0txbufempty, asc0txempty, asc0rxbuffull, asc0errorinterrupt 3 asc1 asc1txbufempty, asc1txempty, asc1rxbuffull, asc1errorinterrupt 15:4 unused unused 16 interrupt0 pin 17 interrupt1 pin table 6.1 interrupt assignments
ST20-GP6 38/123 inputinterrupts register the inputinterrupts register is a read only register. it contains a vector which shows all of the input interrupts, so bit 0 of the read data corresponds to interruptin0 , bit 1 corresponds to interruptin1 . low power controller support registers the interrupt level controller has 2 additional registers to support the low power controller (see chapter 11 on page 66). the external interrupts can be used to provide a wake-up from power- down mode. the intlpenable register can be programmed for each interrupt to cause the interrupt to wake-up the ST20-GP6 from power-down mode. the wake-up occurs when the interrupt goes either high or low, depending on the setting of the respective bit in the intactivehigh register. intlpenable the intlpenable register can be set to enable a wake-up from power-down mode when the inter- rupt occurs. intpriority interrupt level controller base address + #00 to #1c read/write bit bit field function 2:0 intpriority determines the priority of each interrupt input. intpriority2:0 asserts output interrupt 000 0 (lowest priority) 001 1 010 2 011 3 100 4 101 5 110 6 111 7 (highest priority) table 6.2 intpriority register format - 1 register per interrupt inputinterrupts interrupt level controller base address + #48 read only bit bit field function 1:0 interruptin-0 input interrupt levels. table 6.3 inputinterrupts register format
ST20-GP6 39/123 intactivehigh the setting of the intactivehigh register determines whether the wake-up occurs when the inter- rupt goes high or low, assuming the interrupt has been enabled to cause a wake-up in the intl- penable register. intlpenable interrupt level controller base address + #50 read/write bit bit field function 0 int0lpenable enable external interrupt0 for low power controller. 0 interrupt0 masked from the low power controller 1 interrupt0 enabled to cause a wake-up from power down mode 1 int1lpenable enable external interrupt1 for low power controller. 0 interrupt1 masked from the low power controller 1 interrupt1 enabled to cause a wake-up from power down mode table 6.4 intlpenable register format intactivehigh interrupt level controller base address + #4c read/write bit bit field function 0 int0activehigh interrupt0 set to be active high or low 0 interrupt0 goes low the ST20-GP6 wakes up from power down mode. 1 interrupt0 goes high the ST20-GP6 wakes up from power down mode. 1 int1activehigh interrupt1 set to be active high or low 0 interrupt1 goes low the ST20-GP6 wakes up from power down mode. 1 interrupt1 goes high the ST20-GP6 wakes up from power down mode. table 6.5 intactivehigh register format
ST20-GP6 40/123 7 instruction set this chapter provides information on the st20-c2 instruction set. it contains tables listing all the instructions, and where applicable provides details of the number of processor cycles taken by an instruction. the instruction set has been designed for simple and effi cient compilation of high-level languages. all instructions have the same format, designed to give a compact representation of the operations occurring most frequently in programs. each instruction consists of a single byte divided into two 4-bit parts. the four most signifi cant bits (msb) of the byte are a function code and the four least signifi cant bits (lsb) are a data value, as shown in figure 7.1. figure 7.1 instruction format for further information on the instruction set refer to the st20c2/c4 instruction set manual (docu- ment number 72-trn-273). 7.1 instruction cycles timing information is available for some instructions. however, it should be noted that many instructions have ranges of timings which are data dependent. where included, timing information is based on the number of clock cycles assuming any memory accesses are to 2 cycle internal memory and no other subsystem is using memory. actual time will be dependent on the speed of external memory and memory bus availability. note that the actual time can be increased by: 1 the instruction requiring a value on the register stack from the fi nal memory read in the pre- vious instruction the current instruction will stall until the value becomes available. 2 the fi rst memory operation in the current instruction can be delayed while a preceding memory operation completes - any two memory operations can be in progress at any time, any further operation will stall until the first completes. 3 memory operations in current instructions can be delayed by access by instruction fetch or subsystems to the memory interface. 4 there can be a delay between instructions while the instruction fetch unit fetches and par- tially decodes the next instruction this will be the case whenever an instruction causes the instruction flow to jump. note that the instruction timings given refer to `standard' behavior and may be different if, for exam- ple, traps are set by the instruction. function data 7430
ST20-GP6 41/123 7.2 instruction characteristics table 7.3 gives the basic function code of each of the primary instructions. where the operand is less than 16, a single byte encodes the complete instruction. if the operand is greater than 15, one prefi x instruction ( pfi x ) is required for each additional four bits of the operand. if the operand is neg- ative the fi rst prefi x instruction will be nfi x . examples of pfi x and nfi x coding are given in table 7.1. any instruction which is not in the instruction set tables is an invalid instruction and is fl agged ille- gal, returning an error code to the trap handler, if loaded and enabled. the notes column of the tables indicates the features of an instruction as described in table 7.2 . mnemonic function code memory code ldc #3 #4 #43 ldc #35 is coded as pfi x #3 #2 #23 ldc #5 #4 #45 ldc #987 is coded as pfi x #9 #2 #29 pfi x #8 #2 #28 ldc #7 #4 #47 ldc -31 ( ldc #ffffffe1) is coded as nfi x #1 #6 #61 ldc #1 #4 #41 table 7.1 prefix coding ident feature e instruction can set an integererror trap l instruction can cause a loadtrap trap s instruction can cause a storetrap trap o instruction can cause an overfl ow trap i interruptible instruction a instruction can be aborted and later restarted. d instruction can deschedule t instruction can timeslice table 7.2 instruction features
ST20-GP6 42/123 7.3 instruction set tables function code memory code mnemonic processor cycles name notes 0 0x j 5 jump d, t 1 1x ldlp 1 load local pointer 2 2x pfi x 0 to 1 prefi x 3 3x ldnl 2 load non-local 4 4x ldc 1 load constant 5 5x ldnlp 1 load non-local pointer 6 6x nfi x 0 to 1 negative prefi x 7 7x ldl 1 load local 8 8x adc 1 add constant o 9 9x call 8 call a ax cj 1 or 5 conditional jump b bx ajw 2 adjust workspace c cx eqc 1 equals constant d dx stl 1 store local e ex stnl 2 store non-local f fx opr 0 operate table 7.3 primary functions memory code mnemonic processor cycles name notes 22fa testpranal 2 test processor analyzing 23fe saveh 3 save high priority queue registers 23fd savel 3 save low priority queue registers 21f8 sthf 1 store high priority front pointer 25f0 sthb 1 store high priority back pointer 21fc stlf 1 store low priority front pointer 21f7 stlb 1 store low priority back pointer 25f4 sttimer 2 store timer 2127fc lddevid 1 load device identity 27fe ldmemstartval 1 load value of memstart address table 7.4 processor initialization operation codes
ST20-GP6 43/123 memory code mnemonic processor cycles name notes 24f6 and 1 and 24fb or 1 or 23f3 xor 1 exclusive or 23f2 not 1 bitwise not 24f1 shl 1 shift left 24f0 shr 1 shift right f5 add 1 add a, o fc sub 1 subtract a, o 25f3 mul 4 multiply a, o 27f2 fmul 6 fractional multiply a, o 22fc div 5 to 37 divide a, o 21ff rem 5 to 40 remainder a, o f9 gt 1 greater than a 25ff gtu 1 greater than unsigned a f4 diff 1 difference 25f2 sum 1 sum f8 prod 4 product a 26f8 satadd 2 saturating add a 26f9 satsub 2 saturating subtract a 26fa satmul 5 saturating multiply a table 7.5 arithmetic/logical operation codes
ST20-GP6 44/123 memory code mnemonic processor cycles name notes 21f6 ladd 2 long add a, o 23f8 lsub 2 long subtract a, o 23f7 lsum 2 long sum 24ff ldiff 2 long diff 23f1 lmul 5 to 6 long multiply a 21fa ldiv 5 to 39 long divide a, o 23f6 lshl 2 long shift left a 23f5 lshr 2 long shift right a 21f9 norm 2 to 5 normalize a 26f4 slmul 5 signed long multiply a, o 26f5 sulmul 5 signed times unsigned long multiply a, o table 7.6 long arithmetic operation codes memory code mnemonic processor cycles name notes f0 rev 1 reverse 23fa xword 4 extend to word a 25f6 cword 3 check word a, e 21fd xdble 2 extend to double 24fc csngl 3 check single a, e 24f2 mint 1 minimum integer 25fa dup 1 duplicate top of stack 27f9 pop 1 pop processor stack 68fd reboot 1 reboot table 7.7 general operation codes
ST20-GP6 45/123 memory code mnemonic processor cycles name notes f2 bsub 1 byte subscript fa wsub 1 word subscript 28f1 wsubdb 1 form double word subscript 23f4 bcnt 1 byte count 23ff wcnt 1 word count f1 lb 1 load byte 23fb sb 2 store byte 24fa move move message i table 7.8 indexing/array operation codes memory code mnemonic processor cycles name notes 22f2 ldtimer 1 load timer 22fb tin timer input i 24fe talt 3 timer alt start 25f1 taltwt timer alt wait d, i 24f7 enbt 2 to 8 enable timer 22fe dist disable timer i table 7.9 timer handling operation codes
ST20-GP6 46/123 memory code mnemonic processor cycles name notes f7 in input message d fb out output message d ff outword output word d fe outbyte output byte d 24f3 alt 2 alt start 24f4 altwt 4 to 7 alt wait d 24f5 altend 9 alt end 24f9 enbs 1 to 2 enable skip 23f0 diss 1 disable skip 21f2 resetch 3 reset channel 24f8 enbc 2 to 5 enable channel 22ff disc 2 to 7 disable channel table 7.10 input and output operation codes memory code mnemonic processor cycles name notes 22f0 ret 3 return 21fb ldpi 1 load pointer to instruction 23fc gajw 3 general adjust workspace f6 gcall 6 general call 22f1 lend 5 to 8 loop end t table 7.11 control operation codes memory code mnemonic processor cycles name notes fd startp 5 start process f3 endp 4 to 6 end process d 23f9 runp 3 run process 21f5 stopp 2 stop process 21fe ldpri 1 load current priority table 7.12 scheduling operation codes
ST20-GP6 47/123 memory code mnemonic processor cycles name notes 21f3 csub0 2 check subscript from 0 a, e 24fd ccnt1 3 check count from 1 a, e 22f9 testerr 2 test error false and clear 21f0 seterr 2 set error 25f5 stoperr 2 to 3 stop on error (no error) d 25f7 clrhalterr 1 clear halt-on-error 25f8 sethalterr 1 set halt-on-error 25f9 testhalterr 2 test halt-on-error table 7.13 error handling operation codes memory code mnemonic processor cycles name notes 25fb move2dinit 3 initialize data for 2d block move 25fc move2dall 2d block copy i 25fd move2dnonzero 2d block copy non-zero bytes i 25fe move2dzero 2d block copy zero bytes i table 7.14 2d block move operation codes memory code mnemonic processor cycles name notes 27f4 crcword 36 calculate crc on word a 27f5 crcbyte 12 calculate crc on byte a 27f6 bitcnt 3 count bits set in word a 27f7 bitrevword 2 reverse bits in word 27f8 bitrevnbits 2 reverse bottom n bits in word a table 7.15 crc and bit operation codes
ST20-GP6 48/123 memory code mnemonic processor cycles name notes 27f3 cfl err 3 check fl oating point error e 29fc fptesterr 1 load value true (fpu not present) 26f3 unpacksn 10 unpack single length fl oating point number a 26fd roundsn 7 round single length fl oating point number a 26fc postnormsn 9 post-normalize correction of single length fl oat- ing point number a 27f1 ldinf 1 load single length infi nity table 7.16 floating point support operation codes memory code mnemonic processor cycles name notes 2cf7 cir 3 check in range a, e 2cfc ciru 3 check in range unsigned a, e 2bfa cb 3 check byte a, e 2bfb cbu 2 check byte unsigned a, e 2ffa cs 3 check sixteen a, e 2ffb csu 2 check sixteen unsigned a, e 2ff8 xsword 3 sign extend sixteen to word a 2bf8 xbword 3 sign extend byte to word a table 7.17 range checking and conversion instructions memory code mnemonic processor cycles name notes 2cf1 ssub 1 sixteen subscript 2cfa ls 1 load sixteen 2cf8 ss 2 store sixteen 2bf9 lbx 1 load byte and sign extend 2ff9 lsx 1 load sixteen and sign extend table 7.18 indexing/array instructions
ST20-GP6 49/123 memory code mnemonic processor cycles name notes 2ff0 devlb 3 device load byte a 2ff2 devls 3 device load sixteen a 2ff4 devlw 3 device load word a 62f4 devmove device move i 2ff1 devsb 3 device store byte a 2ff3 devss 3 device store sixteen a 2ff5 devsw 3 device store word a table 7.19 device access instructions memory code mnemonic processor cycles name notes 60f5 wait 5 to 11 wait d 60f4 signal 7 to 12 signal table 7.20 semaphore instructions memory code mnemonic processor cycles name notes 60f0 swapqueue 4 swap scheduler queue 60f1 swaptimer 5 swap timer queue 60f2 insertqueue 3 to 4 insert at front of scheduler queue 60f3 timeslice 3 to 4 timeslice 60fc ldshadow 6 to 31 load shadow registers a 60fd stshadow 6 to 17 store shadow registers a 62fe restart 20 restart 62ff causeerror 7 to 8 cause error 61ff iret 3 to 11 interrupt return 2bf0 settimeslice 2 set timeslicing status 2cf4 intdis 2 interrupt disable 2cf5 intenb 2 interrupt enable 2cfd gintdis 5 global interrupt disable 2cfe gintenb 5 global interrupt enable table 7.21 scheduling support instructions
ST20-GP6 50/123 memory code mnemonic processor cycles name notes 26fe ldtraph 12 load trap handler l 2cf6 ldtrapped 12 load trapped process status l 2cfb sttrapped 12 store trapped process status s 26ff sttraph 12 store trap handler s 60f7 trapenb 4 trap enable 60f6 trapdis 4 trap disable 60fb tret 8 to 10 trap return table 7.22 trap handler instructions memory code mnemonic processor cycles name notes 68fc ldprodid 1 load product identity 63f0 nop 1 no operation table 7.23 processor initialization and no operation instructions memory code mnemonic processor cycles name notes 64ff clockenb 2 clock enable 64fe clockdis 2 clock disable 64fd ldclock 2 load clock 64fc stclock 2 store clock table 7.24 clock instructions
ST20-GP6 51/123 8 memory map the ST20-GP6 processor memory has a 32-bit signed address range. words are addressed by 30-bit word addresses and a 2-bit byte-selector identifi es the bytes in the word. memory is divided into 4 banks which can each have different memory characteristics and can be used for different purposes. in addition, on-chip peripherals can be accessed via the device access instructions (see table 7.19). the bottom 16 kbytes of the internal sram are powered from the battery backup supply. various memory locations at the bottom and top of memory are reserved for special system purposes. there is also a default allocation of memory banks to different uses. note that the ST20-GP6 uses 30 bits of addressing internally, but addresses a20-a29 are not brought out to external pins. address bits a30 and a31 are decoded internally for use as bank selects. 8.1 system memory use the ST20-GP6 has a signed address space where the address ranges from minint (#80000000) at the bottom to maxint (#7fffffff) at the top. the ST20-GP6 has an area of 64 kbytes of sram at the bottom of the address space provided by on chip memory. the bottom of this area is used to store various items of system state. these addresses should not be accessed directly but via the appropriate instructions. near the bottom of the address space there is a special address memstart . memory above this address is for use by user programs while addresses below it are for private use by the processor and used for subsystem channels and trap handlers. the address of memstart can be obtained via the ldmemstartval instruction. 8.1.1 subsystem channels memory each dma channel between the processor and a subsystem is allocated a word of storage below memstart . this is used by the processor to store information about the state of the channel. this information should not normally be examined directly, although debugging kernels may need to do so. 8.1.2 trap handlers memory the area of memory reserved for trap handlers is broken down hierarchically. full details on trap handlers is given in see section 4.6 on page 23. ? each high/low process priority has a set of trap handlers. ? each set of trap handlers has a handler for each of the four trap groups (refer to section 4.6.1). ? each trap group handler has a trap handler structure and a trapped process structure. ? each of the structures contains four words, as detailed in section 4.6.3.
ST20-GP6 52/123 the contents of these addresses can be accessed via ldtraph , sttraph , ldtrapped and sttrapped instructions. 8.2 boot rom there is 128k bytes of mask rom on-chip. this is mapped to the upper 128k of bank 3 (addresses #7ffe0000 to #7fffffff). if mask rom is not programmed, internal rom is disabled and external rom is used. when the processor boots from rom, it jumps to a boot program held in rom with an entry point 2 bytes from the top of memory at #7ffffffe. these 2 bytes are used to encode a negative jump of up to 256 bytes down in the rom program. for large rom programs it may then be necessar y to encode a longer negative jump to reach the start of the routine. 8.3 internal peripheral space on-chip peripherals are mapped to addresses in the address range #00000000 to #3fffffff). they can only be accessed by the device access instructions (see table 7.19). when used with addresses in this range, the device instructions access the on-chip peripherals rather than external memory. for all other addresses the device instructions access memory. standard load/store instructions to these addresses will access external memory. each on-chip peripheral occupies a 4k block, see the following memory map.
ST20-GP6 53/123 address use memory bank maxint #7fffffff bank 3 bootentry #7ffffffe user code and boot rom #40000000 reserved bank 2 #2000e000 dsp controller peripheral (registers accessed via cpu device accesses) #2000c000 pio b controller peripheral (registers accessed via cpu device accesses) #2000a000 pio a controller peripheral (registers accessed via cpu device accesses) #20008000 asc1 controller peripheral (registers accessed via cpu device accesses) #20006000 asc0 controller peripheral (registers accessed via cpu device accesses) #20004000 real-time clock/watchdog timer peripheral (registers accessed via cpu device accesses) #20002000 interrupt level controller peripheral (registers accessed via cpu device accesses) #20001000 interrupt and low power controller peripheral (registers accessed via cpu device accesses) #20000000 reserved #00004000 diagnostic controller(registers accessed via cpu device accesses) #00003000 external memory interface(registers accessed via cpu device accesses) #00002000 reserved #00000000 user code/data/stack bank 1 #c0000000 bank 0 start of external memory #81000000 memstart #80000140 #80000130 low priority scheduler trapped process #80000120 low priority scheduler trap handler #80000110 low priority systemoperations trapped process #80000100 low priority systemoperations trap handler #800000f0 low priority error trapped process #800000e0 low priority error trap handler #800000d0 low priority breakpoint trapped process #800000c0 low priority breakpoint trap handler #800000b0 high priority scheduler trapped process #800000a0 high priority scheduler trap handler figure 8.1 ST20-GP6 internal peripheral map
ST20-GP6 54/123 #80000090 high priority systemoperations trapped process bank 0 #80000080 high priority systemoperations trap handler #80000070 high priority error trapped process #80000060 high priority error trap handler #80000050 high priority breakpoint trapped process trapbase #80000040 high priority breakpoint trap handler #8000003c reserved #8000001c #80000018 #80000014 dsp module dma channel #80000010 reserved #8000000c #80000008 #80000004 minint #80000000 address use memory bank figure 8.1 ST20-GP6 internal peripheral map
ST20-GP6 55/123 9 memory subsystem the memory system consists of sram and a programmable memory interface. the specifi c details on the operation of the memory interface are described separately in chapter 10. 9.1 sram there is an internal memory module of 64 kbytes of sram. the internal sram is mapped into the base of the memory space from minint (#80000000) extending upwards. this memory can be used to store on-chip data, stack or code for time critical routines. optional external ram, if fi tted, is addressed from #81000000. 9.2 rom there is 128 kbytes of on-chip rom for application code.
ST20-GP6 56/123 10 programmable memory interface the ST20-GP6 programmable memory interface has a 16 bit data bus and provides glueless support for up to four banks of sram memory. suffi cient confi guration options are provided to enable the interface to be used with a wide variety of sram speeds, permitting systems to be built with optimum price/performance trade-offs. the programmable memory interface is also referred to as the external memory interface (emi). the emi provides confi guration information for four independent banks of external memory devices. the addresses of these bank boundar ies are hard wired to give each bank one quarter of the address space of the machine. bank 0 occupies the lowest quarter of the [signed] address space, bank 3 is the highest, see figure 10.1. the confi guration is held in memory mapped registers within the emi. each bank has 64 bits to hold confi guration data. this data is accessed as four 16-bit accesses. the emi confi guration software ensures that the confi guration of a bank is consistent and works with all devices in the bank before any access to that bank. default confi gurations on start-up (see adefault confi gurationo on page 65) allow the slowest memory to be accessed. four confi guration control registers (one for each bank) are provided which allow the confi guration data registers to be locked. this prevents an accidental overwrite from destroying the emi confi guration. a confi guration status register is also provided to show which banks have been locked and which banks have been confi gured. the memory map for the confi guration registers within the emi contains 16 x 16-bit data registers each located at word boundary, plus four lock control registers and a global register for status information.
ST20-GP6 57/123 figure 10.1 memory allocation 00000000 7fffffff 80000000 64k internal sram c0000000 40000000 on-chip peripheral registers are mapped into this bank. bank 0 addresses shown are physical addresses. on-chip peripherals subsystem channels traps/ exceptions internal sram 20000000 bank 1 bank 2 bank 3 80000000 memstart 8000ffff 81000000 external memory 7f000000 external memory 128k internal rom emi confi guration diagnostic controller 00003fff 00002000 7ffe0000 reserved reserved 80003fff battery backed ram 00003000 00010000 reserved
ST20-GP6 58/123 10.1 emi signal descriptions the following section describes the functions of the emi pins. note that a signal name prefi xed by not indicates active low. memaddr1-19 external address bus. the ST20-GP6 uses 30 bits of addressing internally but only the bottom 18 bits are brought out to external pins ( memaddr2-19 ); memaddr1 is generated by the emi. memaddr1-19 is valid and constant for the whole duration of an external access. the memory locations in each bank can be accessed at multiple addresses, as bits 20-29 are ignored when making external accesses. memdata0-15 external data bus. the data bus may be confi gured to be either 8 or 16 bits wide on a per bank basis. memdata0 is always the least signifi cant bit. memdata7 is the most signifi cant bit in 8-bit mode and memdata15 is the most signifi cant bit in 16-bit mode. when performing a write access to a bank confi gured to be 8-bits wide, memdata8-15 are held in a high-impedance state for the duration of the access; memdata0-7 behave according to the confi guration parameters as specifi ed in section 10.4. when making a write to a bank confi gured to be 16-bits wide, memdata0-15 behave according to the configuration parameters. notmemce0-3 chip enable strobes, one per bank. the notmemce0-3 strobe corresponding to the bank being accessed will be active on both reads and writes to that bank. notmemoe0 output enable strobe. this strobe is shared between all four banks. the notmemoe0 strobe will be active only on reads to the bank. notmembe0-1 byte enable strobes to select bytes within a 16-bit half-word. these strobes are shared between all four banks. notmembe0 always corresponds to data on memdata0-7 whether the bus is currently 8 or 16 bits wide. when the emi is accessing a bank confi gured to be 16 bits wide, notmembe1 corresponds to memdata8-15 . when the emi is accessing a bank confi gured to be 8 bits wide, notmembe1 becomes address bit 0 and follows the timing of memaddr1-19 for that bank. memwait halt external access. the emi samples memwait at or just after the midpoint of an access. if memwait is sampled high, the access is stalled. memwait will then continue to be sampled and the access proceeds when memwait is sampled low. the action of memwait may be disabled by software, see section 10.3. no mechanism is provided to abort an access; if memwait is held high too long the emi will become a contentious resource and may stall the ST20-GP6. memreadnotwrite the memreadnotwrite pin indicates if the current access is a read or a write. buswidth this signal is sampled immediately after reset and determines the initial bus width of all banks after reset.
ST20-GP6 59/123 10.2 external accesses figure 10.2 shows the generic emi activity during an access and the confi gurable parameters are given in table 10.2. buswidth meaning 0 16-bit external bus on reset. 1 8-bit external bus on reset. table 10.1 buswidth encoding figure 10.2 generic access read data latch point busrelease time data drive delay cee1 time cee2 time oee1 time bee1 time be e2 time accesscycletime memaddress notmemce notmemoe notmembe memdata (write) memdata (read) oee2time memreadnotwrite write constant high for reads
ST20-GP6 60/123 10.3 memwait the memwait pin is sampled on each processor clock cycle during accesses to banks. in cycles when it is sampled high, the external access is halted and the strobe state does not change. memwait suspends the state of the emi in the cycle after it is sampled high. the state remains suspended until memwait is sampled low. any strobe edges scheduled to occur in the cycle after memwait is sampled will not occur. strobe edges scheduled to occur on the same edge as memwait is sampled are not affected. figure 10.3 and figure 10.4 show the extension of the external memory cycle and the delaying of strobe transitions. note, the clock shown in the fi gures is the internal on-chip clock and is provided as a guide to show the minimum setup time of memwait relative to the strobes. note that memwait is ignored if it is sampled high on the last cycle of the access. name programmable value 16.368 mhz 32.736 mhz accesstime 2 cycles + 0 to 15 cycles 122 to 1039 ns 61 to 519 ns busrelease- time 0 to 3 cycles 0 to 183 ns 0 to 92 ns datadrivedelay 0 to 7 phases after start of access cycle 0 to 214 ns 0 to 107 ns cee1time falling edge of ce: 0 to 3 phases after start of access cycle 0 to 92 ns 0 to 46 ns cee2time rising edge of ce: 0 to 3 phases before end of access cycle 0 to 92 ns 0 to 46 ns oee1time falling edge of oe: 0 to 3 phases after start of access cycle 0 to 92 ns 0 to 46 ns oee2time rising edge of oe: 0 to 3 phases before end of access cycle. 0 to 92 ns 0 to 46 ns bee1time falling edge of be: 0 to 3 phases after start of access cycle 0 to 92 ns 0 to 46 ns bee2time rising edge of be: 0 to 3 phases before end of access cycle 0 to 92 ns 0 to 46 ns latchpoint 0 = 1 cycle before end of access cycle. 1 = end of access cycle. 0 to 61 ns 0 to 30 ns table 10.2 parameters for generic access
ST20-GP6 61/123 figure 10.3 strobe activity without memwait figure 10.4 strobe activity with memwait note, strobe refers to the emi strobe signals notmemoe , notmemce and notmembe . clock memwait strobe1 strobe2 strobe3 clock memwait asserted wait cycle memwait strobe1 strobe2 strobe3
ST20-GP6 62/123 10.4 emi configuration register s the following is a summary of the confi guration registers format. times are programmed in cycles or phases: a cycle is one clock cycle, a phase is half a clock cycle. there are 4 data confi guration registers for each of the emi banks. the base addresses for the emi registers is #00002000 . emiconfigdata0bank0-3 the emiconfigdata0bank0-3 registers contain confi guration data for each of the emi banks. the format of each of the emiconfigdata0 registers is shown in table 10.3. emiconfigdata0bank0-3 emi base address + #00, #10, #20, #30 read/write bit bit field function units 2:0 devicetype device type. sets the format of the confi guration register. this must be set to 001 on the ST20-GP6. 001 = sram/peripheral - 4:3 portsize port size 00 = reserved 01 = reserved 10 = 16 bit 11 = 8 bit - 6:5 beactive notmembe active, see table 10.4 below. - 8:7 oeactive notmemoe active, see table 10.4 below. - 10:9 ceactive notmemce active, see table 10.4 below. - 12:11 busreleasetime duration bus release time. 0 to 3 cycles cycles 15:13 datadrivedelay drive delay of data bus for writes. 0 to 7 phases phases table 10.3 emiconfigdata0 register format - 1 per bank ce/oe/be activecode strobe activity 00 inactive 01 active during read only 10 active during write only 11 active during read and write table 10.4 strobe configuration
ST20-GP6 63/123 emiconfigdata1bank0-3 the emiconfigdata1bank0-3 registers contain confi guration data for each of the emi banks. the format of each of the emiconfigdata1 registers is shown in table 10.5. emiconfigdata2bank0-3 the emiconfigdata2bank0-3 registers contain confi guration data for each of the emi banks. the format of each of the emiconfigdata2 registers is shown in table 10.6. emiconfigdata1bank0-3 emi base address + #04, #14, #24, #34 read/write bit bit field function units 1:0 bee2timeread rising edge of notmembe . 0 to 3 phases before end of access cycle phases 3:2 bee1timeread falling edge of notmembe . 0 to 3 phases after start of access cycle phases 5:4 oee2timeread rising edge of notmemoe . 0 to 3 phases before end of access cycle phases 7:6 oee1timeread falling edge of notmemoe . 0 to 3 phases after start of access cycle phases 9:8 cee2timeread rising edge of notmemce . 0 to 3 phases before end of access cycle phases 11:10 cee1timeread falling edge of notmemce . 0 to 3 phases after start of access cycle phases 15:12 accesstimeread 2 cycles + 0 to 15 cycles cycles table 10.5 emiconfigdata1 register format - 1 per bank emiconfigdata2bank0-3 emi base address + #08, #18, #28, #38 read/write bit bit field function units 1:0 bee2timewrite rising edge of notmembe . 0 to 3 phases before end of access cycle phases 3:2 bee1timewrite falling edge of notmembe . 0 to 3 phases after start of access cycle phases 5:4 oee2timewrite rising edge of notmemoe . 0 to 3 phases before end of access cycle phases 7:6 oee1timewrite falling edge of notmemoe . 0 to 3 phases after start of access cycle phases 9:8 cee2timewrite rising edge of notmemce . 0 to 3 phases before end of access cycle phases 11:10 cee1timewrite falling edge of notmemce . 0 to 3 phases after start of access cycle phases 15:12 accesstimewrite 2 cycles + 0 to 15 cycles cycles table 10.6 emiconfigdata2 register format - 1 per bank
ST20-GP6 64/123 emiconfigdata3bank0-3 the emiconfigdata2bank0-3 registers contain confi guration data for each of the emi banks. the format of each of the emiconfigdata3 registers is shown in table 10.7 . emiconfiglockbank0-3 registers the emiconfiglockbank0-3 registers (one for each bank) allow the confi guration data registers to be locked. this prevents an accidental overwrite from destroying the emi confi guration. a system reset clears these registers. emiconfigstatus register the emiconfigstatus register is provided to indicate which registers have been written to and the status of the lock bits. table 10.9 shows the format of the emiconfigstatus register. emiconfigdata3bank0-3 emi base address + #0c, #1c, #2c, #3c read/write bit bit field function 0 latchpoint position of latch point in cycle. 0 = 1 cycle before end of access cycle 1 = end of access cycle 15:1 reserved, write 0. table 10.7 emiconfigdata3 register format - 1 per bank emiconfigloc kbank0-3 emi base address + #40, #44, #48, #4c write only bit bit field function 0 configloc k write protection bit. when set, emiconfigdata0-3 for the bank is read only. table 10.8 emiconfiglock register format - 1 per bank emiconfigstatus emi base address + #50 read only bit bit field function 0 writtenbank0 bank 0 confi guration data registers have been written to. 1 writtenbank1 bank 1confi guration data registers have been written to. 2 writtenbank2 bank 2 confi guration data registers have been written to. 3 writtenbank3 bank 3 confi guration data registers have been written to. 4 writelockbank0 emiconfigdata0-3bank0 registers are write protected. 5 writelockbank1 emiconfigdata0-3bank1 registers are write protected. 6 writelockbank2 emiconfigdata0-3bank2 registers are write protected. 7 writelockbank3 emiconfigdata0-3bank3 registers are write protected. table 10.9 emiconfigstatus register format
ST20-GP6 65/123 10.5 boot source the cpu boots from rom, unless the diagnostic control unit (dcu) is confi gured (via the tap) to start in diagnostic mode: in which case code is loaded, and the cpu booted, via the dcu. 10.6 default configuration the default confi guration is loaded into all four banks on reset. it allows the emi to read data from a slow rom memory. the default parameters are given in table 10.10. . parameter default value datadrivedelay 101 (5 phases) busreleasetime 10 (2 cycles) ceactive 01 (active during read only) oeactive 01 (active during read only) beactive 00 (inactive) portsize determined by the buswidth signal devicetype 001 (sram/peripheral) accesstimeread 1000 (8+2=10 cycles) cee1timeread 00 (0 phases) cee2timeread 00 (0 phases) oee1timeread 00 (0 phases) oee2timeread 00 (0 phases) latchpoint 0 (1 cycle before end of access cycle) table 10.10 default confi guration
ST20-GP6 66/123 11 low power controller 11.1 low power control the ST20-GP6 is designed for 0.35 micron, 3.3v cmos technology and runs at speeds of up to 50 mhz. 3.3v operation provides reduced power consumption internally and allows the use of low power peripherals. in addition, to further enhance the potential for battery operation, a low power power-down mode is available. the different power levels of the ST20-GP6 are listed below. ? operating power e power consumed during functional operation. ? stand-by power e power consumed during little or no activity. the cpu is idle but ready to immediately respond to an interrupt/reschedule. ? power-down e internal clocks are stopped and power consumption is signifi cantly reduced. functional operation is stalled. normal functional operation can be resumed from previous state as soon as the clocks are stable. all internal logic is static so no information is lost during power down. ? power to most of the chip removed e only the real time clock supply ( rtcvdd ) power on. 11.1.1 power-down mode power-down mode can be achieved in one of two ways, as listed below. ? availability of direct clock input e this allows external control of clocking directly and thus direct control of power consumption. ? internal global system clock may be stopped e in this case the external clock remains run- ning. this mechanism allows the pll to be kept running (if desired) so that wake up from low power mode will be fast. the low power timer and alarm are provided to control the duration for which the global clock gen- eration is stopped during low power mode. the timer and alarm registers can be set by the device store instructions and read by the device load instructions. the ST20-GP6 enters power-down when: ? the low power alarm is programmed and started, via confi guration registers, providing there are no interrupts pending. the ST20-GP6 exits power-down when: ? there is specifi c external pin activity ( interrupt pin); ? the low power alarm counter reaches zero. in power-down mode the processor and all peripherals are stopped, including the external memory controller and optionally the pll. effectively the internal clock is stopped and functional operation is stalled. on restart the clock is restarted and the chip resumes normal functional operation.
ST20-GP6 67/123 low power timer the timer keeps track of real time, even when the internal clocks are stopped. the timer is a 64-bit counter which runs off an external clock ( lowpowerclockin ). this clock rate must not be more than one eighth of the system clock rate. low power alarm there is also a 40-bit low power alarm counter. a write to the lpalarmstart register starts the low power alarm counter and the ST20-GP6 enters low power mode. when the counter has counted down to zero, assuming no other valid wake-up sources occur fi rst, the ST20-GP6 exits low power mode and the global clocks are turned back on. whilst the clocks are turned off the lowpowersta- tus pin is high, otherwise it is low. 11.2 low power configuration register s the low power controller is allocated a 4k block of memory in the internal peripheral address space. information on low power mode is stored in registers as detailed in the following section. the registers can be examined and set by the devlw (device load word) and devsw (device store word) instructions, see table 7.19 on page 49. note, they can not be accessed using memory instructions. lptimerls and lptimerms the lptimerls and lptimerms registers are the least signifi cant word and most signifi cant word of the lptimer register. this enables the least signifi cant or most signifi cant word to be written independently without affecting the other word. table 11.1 lptimerls register format table 11.2 lptimerms register format when the lptimer register is written, the low power timer is stopped and the new value is avail- able to be written to the low power timer. lptimerstart a write to the lptimerstart register starts the low power timer counter. the counter is stopped and the lptimerstart register reset if either counter word ( lptimerls and lptimerms ) is writ- ten. lptimerls lpc base address + #400 read/write bit bit field function 31:0 lptimerls least signifi cant word of the low power timer. lptimerms lpc base address + #404 read/write bit bit field function 31:0 lptimerms most signifi cant word of the low power timer.
ST20-GP6 68/123 note, setting the lptimerstart register to zero does not stop the timer. table 11.3 lptimerstart register format lpalarmls and lpalarmms the lpalarmls and lpalarmms registers are the least signifi cant word and most signifi cant word of the lpalarm register. this is used to program the low power alarm. table 11.4 lpalarmls register format table 11.5 lpalarmms register format lpalarmstart a write to the lpalarmstart register starts the low power alarm counter. the counter is stopped and the lpstart register reset if either counter word ( lptimerls and lptimerms ) is written. table 11.6 lpalarmstart register format lpsyspll the lpsyspll register controls the system clock pll operation when low power mode is entered. this allows a compromise between wake-up time and power consumption during stand-by. table 11.7 lpsyspll register format lptimerstart lpc base address + #408 write bit bit field function 0 lptimerstart a write to this bit starts the low power timer counter. lpalarmls lpc base address + #410 read/write bit bit field function 31:0 lpalarmls least signifi cant word of the low power alarm. lpalarmms lpc base address + #414 read/write bit bit field function 7:0 lpalarmms most signifi cant word of the low power alarm. lpalarmstart lpc base address + #418 write bit bit field function 0 lpalarmstart a write to this bit starts the low power alarm counter. lpsyspll lpc base address + #420 read/write bit bit field function 1:0 lpsyspll determines the system clock pll when low power mode is entered, as follows: lpsyspll1:0 system clock 00 pll off 01 pll reference on and power on 10 pll reference on and power on 11 pll on
ST20-GP6 69/123 sysratio the sysratio register is a read only register and gives the speed at which the system pll is running. it contains the relevant pll multiply ratio when using the pll, or contains the value `1' when in timesonemode for the pll. table 11.8 sysratio register format sysratio lpc base address + #500 read bit bit field function 1:0 sysratio pll speed, as follows: sysratio pll 0 x4 reserved 1 x1 16.368 mhz 2 x2 32.736 mhz 3 x3 49.104 mhz
ST20-GP6 70/123 12 real time clock and watchdog timer this chapter specifi es the real time clock-calendar (rtc) and watchdog timer (wdt) module for the ST20-GP6. the rtc provides a set of continuously running counters which can be used, with suitable soft- ware, to provide a clock-calendar function. the counter values can be written to set the current time/data. the rtc is clocked by the 32,768 hz low power clock input and has a separate power supply so that it can continue to run when the rest of the chip is powered down. the wdt provides a fail-safe mechanism to reset the chip if the software fails to clear a counter within a given period. 12.1 power supplies there are two supply voltages to the ST20-GP6, these are: the normal operating supply, vdd , and the battery back-up supply, rtcvdd . the rtc/wdt and the oscillator are powered by rtcvdd to enable the rtc contents to be main- tained at minimal power consumption. 12.2 real time clock the rtc contains two counters: a 30 bit milliseconds counter and a 16 bit weeks counter. this allows large time values to be represented to high accuracy. these counters are not reset as the rtc must run continuously. 12.2.1 rtc counters the milliseconds counter increments at 1.024khz. thus, the value does not actually represent mil- liseconds e this must be taken into account by any software using it. the milliseconds counter is modulo the number of milliseconds in 1 week, or 619,315,200 e i.e. 1024 (one second) x 60 (one minute) x 60 (one hour) x 24 (one day) x 7 (one week). the weeks counter is incremented when the milliseconds counter wraps around from 619,315,199 to 0. this is a 16 bit counter; the gps epoch is only defi ned up to 2 10 weeks, so having extra bits here allows the system to handle times later than this. the current value of both counters can be read at any time by the cpu, but care must be taken to handle the end of week carry occurring between two reads. 12.3 watchdog timer the wdt has a counter, clocked to give a nominal 2 second delay. this counter is periodically cleared, under software control, as described below. if the software fails to clear the counter within the 2 second period then a watchdog reset signal ( notwdreset ) is generated to reset the chip. a status fl ag is set by a watchdog reset. this can be used to indicate to application code that the system was reset by the watchdog timer. this status bit is reset only by the notrst input to the chip.
ST20-GP6 71/123 the watchdog timer function is enabled by an external pin ( wdenable ). if this pin is held low, then a watchdog reset will not occur. 12.4 rtc/wdt configuration register s the rtc/wdt has a number of registers which can be accessed by the cpu. the function of these registers is described below. rtcweeks register the rtcweeks register contains the value of the weeks counter. rtcmilliseconds register the rtcmilliseconds register contains the value of the milliseconds counter. rtcload register a write to the rtcload register loads the weeks and milliseconds counters with the values cur- rently set in the rtcweeks and rtcmilliseconds registers. to minimize the possibility of the counters being erroneously updated by rogue software, the counters are only loaded if the correct value (0xa) is written to the rtcload register. this register is cleared when the load takes place. it is also cleared when the system is reset. in addition, the load operation is only enabled if both the milliseconds and weeks registers have had values written to them since the last load of the counters (or since the system was reset). rtcstatus register the rtcstatus register contains rtc status information. to avoid the milliseconds and weeks counters being loaded with inconsistent values, the millisec- onds and weeks registers must not be modifi ed until the update of the counters has completed. to enable software to detect this situation a status bit is provided in the rtcstatus register to indicate rtcweeks rtc/wdt base address + #00 read/write bit bit field function 15:0 rtcweeks value of weeks counter. table 12.1 rtcweeks register format rtcmilliseconds rtc/wdt base address + #04 read/write bit bit field function 29:0 rtcmilliseconds value of milliseconds counter. table 12.2 rtcmilliseconds register format rtcload rtc/wdt base address + #08 write bit bit field function 3:0 rtcload loads the counters with the values set in the weeks and milliseconds registers. write 0x0a. table 12.3 rtcload register format
ST20-GP6 72/123 that an update of the registers is in progress. a new value must not be written to the rtc counters until this status bit clears (up to two rtc clock cycles later). wdtclear registers the watchdog counter is cleared by writing to two registers ( wdtcleara and wdtclearb regis- ters). each of these must have the correct values (0xa and 0x5, respectively) written to them in either order to clear the counter. wdtstatus register the wdtstatus register can be read to determine if the device was reset by the notrst input or by a watchdog time-out. this status bit is reset only by the notrst input to the chip. rtcstatus rtc/wdt base address + #08 read bit bit field function 0 reserved always returns 0. 1 loading indicates whether an update of the registers is in progress. 0 = rtcweeks and rtcmilliseconds registers can be written; 1 = rtc update in progress. rtcweeks and rtcmilliseconds registers cannot be written table 12.4 rtcstatus register format wdtcleara rtc/wdt base address + #10 write bit bit field function 3:0 wdtcleara first wdt clear address. write 0xa. table 12.5 wdtcleara register format wdtclearb rtc/wdt base address + #14 write bit bit field function 3:0 wdtclearb second wdt clear address. write 0x5. table 12.6 wdtclearb register format wdtstatus rtc/wdt base address + #18 read bit bit field function 0 wdtstatus watchdog timer status fl ag. 0 = chip reset normally (by an external notrst ) 1 = chip reset by watchdog timer table 12.7 wdtstatus register format
ST20-GP6 73/123 13 system services the system services module includes the control system, the pll and power control. system services include all the necessary logic to initialize and sustain operation of the device. 13.1 reset, initialization and debug the ST20-GP6 is controlled by a notrst pin which is a global power-on-reset. 13.1.1 power-on reset notrst initializes the device and causes it to enter its boot sequence (see section 13.2 on bootstrap). notrst must be asserted at power-on and held for 10 ms (or at least 8 lowpowerclockin cycles) after both vdd is in range and clockin is stable. when notrst is asserted low, all modules are forced into their power-on reset condition. the clocks are stopped. the rising edge of notrst is internally synchronized before starting the initialization sequence. 13.2 bootstrap the ST20-GP6 can be bootstrapped from external rom or internal rom. when booting from rom, the ST20-GP6 starts to execute code from the top two bytes in external memory, at address #7ffffffe which should contain a backward jump to a program in rom. 13.3 clocks an on-chip phase locked loop (pll) generates all the internal high frequency clocks. the pll is used to generate the internal clock frequencies needed for the cpu. alternatively a direct clock input can provide the system clocks. the internal clock may be turned off (including the pll) enabling power down mode. the ST20-GP6 can be set to operate in timesonemode , which is when the pll is bypassed. dur- ing timesonemode the input clock must be in the range 0 to 30 mhz and should be nominally 50/ 50 mark space ratio. note, the single clock input ( clockin ) must be 16.368 mhz for correct gps operation. 13.3.1 speed select the speed of the internal processor clock is variable in discrete steps. the clock rate at which the ST20-GP6 runs is determined by the logic levels applied on the two speed select lines speedselect0-1 as detailed in table 13.1. the frequency of clockin (fclk) for the speeds given in the table is 16.368 mhz.
ST20-GP6 74/123 the sysratio register, see table 11.8 on page 69, gives the speed at which the system pll is running. it contains the relevant pll multiply ratio when using the pll, or contains the value `1' when in timesonemode for the pll. 13.3.2 clocking sources the real time clock and low power timer and alarm must be clocked at all times by one of the following clocking sources: ? external clock input ( lowpowerclockin ) e this clock must not be more than one eighth of the system clock rate. in this case the lowpowerclockosc pin should not be connected on the board. ? watch crystal, as in figure 13.1. figure 13.1 watch crystal clocking source speedselect1 speedselect0 processorclock speed (mhz) processor cycle time (ns) approximate phase lock loop factor (pllx) 0 0 reserved 0 1 16.368 61.1 timesonemode a a. in timesonemode the pll is disabled to reduce power consumption. 1 0 32.736 30.5 2 1 1 49.104 20.4 3 table 13.1 processor speed selection internal low power clock watch crystal lowpowerclockosc lowpowerclockin (32768 hz) gnd gnd 22 pf 10 pf a b a - this node should have very low capacitance < 10 pf. b - this node must have zero dc load. 330 k w
ST20-GP6 75/123 14 diagnostic controller the st20 diagnostic controller unit (dcu) provides a means for booting the cpu, and for the con- trol and monitoring of all systems on the chip, via the standard ieee 1194.1 test access port. the test access port is described in chapter 23. the dcu includes on-chip hardware with ice (in cir- cuit emulation) and lsa (logic state analyzer) features to facilitate verification and debugging of software running on the on-chip cpu in real time. it is an independent hardware module with a pri- vate link from the host to support real-time diagnostics. 14.1 diagnostic hardware the on-chip diagnostic controller assists in debugging, while reducing or eliminating the intrusion into the target code space, the cpu utilization, and impact on the application. as shown in figure 14.1, the dcu and tap provide a means of connecting a diagnostic host to a target board with a suitable jtag port connector and interface. figure 14.1 debugging hardware the diagnostic controller provides the following facilities for debugging from a host: ? control of target cpu and subsystems including cpu boot; ? hardware breakpoint, watchpoint, datawatch and single instruction step; ? complex trigger sequencing and choice of subsequent actions; ? non-intrusive jump trace and instruction pointer profiling; ? access to the memory of the target while the device is powered up, regardless of the state of the cpu; ? full debugging of rom code. when running multi-tasking code on the target, one or more processes can be single-stepped or stopped while others continue running in real time. in this case, the running threads can be inter- rupted by incoming hardware interrupts, with a low latency. host host interface test access port diagnostic controller st20 logic state analyzer
ST20-GP6 76/123 the host can communicate with the dcu via a private link, using the 5 standard test pins. target software also has access to the diagnostic facilities and access through the dcu to the host memory. a logic state analyzer can be connected to the triggerin and triggerout pins. the response to triggerin and the events that cause a triggerout signal can be controlled by the host or by target software. the diagnostic controller provides debugging facilities with much less impact on the software and target performance. in particular it gives: ? non-intrusive attachment to the host system; ? no intrusion into the performance of the cpu or any subsystems; ? no intrusion into the code space, so the application builder does not need to add a debug- ging kernel; ? no intrusion into any on-chip functional modules, including any communications facilities; ? no functional external connection pins are used. the connections between the diagnostic controller and other on-chip modules and external hard- ware may vary between st20 variants. 14.2 access features 14.2.1 access to target memory and peripheral registers from host full read and write access to the entire on-chip and external memory space is available via the tap. this is independent of the state of the cpu. the dcu cannot directly access confi guration registers in the on-chip peripheral space. however this is possible via the cpu, and for this the cpu must be active with the appropriate handler installed. normally the dcu would initiate a trap, and the trap handler would access the appropri- ate configuration register. by convention, registers in the address range #20000000 to #3fffffff are in the on-chip periph- eral space and can only be accessed by the cpu. registers and memory outside this range are connected to the address bus and can be accessed directly by the dcu. 14.2.2 access from target cpu process the cpu itself can program its own diagnostic controller. further access may be explicitly pre- vented by the lock mechanism so that the application being debugged cannot interfere with the breakpoint and watchpoint settings. when the breakpoint or watchpoint match occurs, then the diagnostic controller may release the lock according to settings in the control register. 14.2.3 access to host memory from target if the target cpu accesses any address in the top half of the dcu memory space, then these accesses are mapped on to host memory via the tap as target initiated peek and poke messages. peek accesses and poke accesses are specifi cally enabled by separate property bits.
ST20-GP6 77/123 14.3 software debugging features 14.3.1 control of the target cpu including boot various state information about the target cpu may be monitored and the cpu may be controlled from the diagnostic controller via the tap. the control of the cpu extends to stalling, forcing a trap and booting. 14.3.2 non-intrusive iptr profiling a copy of the iptr is visible as a read-only register in the diagnostic controller. this register may be read at any time. reading this register is not intrusive on the cpu or its memory space. 14.3.3 events support is provided by the diagnostic controller to trigger actions when certain predefi ned events occur. breakpoint the function of the breakpoint is to break before the instruction is executed, but only if it really was going to be executed. a 32-bit comparator is used to compare the breakpoint register against the instruction pointer of the next instruction to be executed. the matched instruction is not executed and the cpu state, including all cpu registers, is defi ned as at the start of the instruction. the pre- vious instruction is run to completion. breakpoint range the function of a breakpoint range is equivalent to any single breakpoint but where the breakpoint address can be anywhere within a range of addresses bounded by lower and upper register val- ues. watchpoint the function of a watchpoint is to trigger after a memory access is made to an address within the range specifi ed by a pair of 32-bit registers. the cpu pipeline architecture allows for the cpu to continue execution of instructions without necessarily waiting for a write access to complete. so, by the time a watchpoint violation has been detected, the cpu may have executed a number of instructions after the instruction which caused the violation. if the subsequent action is to stall the cpu or to take a hardware trap, then the last instruction executed before the stall or trap may not be the instruction which caused the violation. datawatch the function of a datawatch is to trigger after a data value specifi ed in one 32-bit register is written to a memory word address specifi ed in another 32-bit register. the subsequent action is equivalent to a watchpoint. scheduling events various scheduling events can be detected. choice of subsequent actions following a watchpoint match, or any other condition detectable by the diagnostic controller, the subsequent action may be programmed to be one of the following: ? stall the cpu, i.e. inhibit further instructions from being executed by the cpu;
ST20-GP6 78/123 ? wait until the end of the current instruction, then signal a hardware trap; ? signal an immediate hardware trap; ? continue without intrusion. in addition, the diagnostic controller may take any combination of the following actions: ? signal on triggerout to a logic state analyzer; ? send a triggered message via the tap to the host; ? unlock access by the target cpu. 14.3.4 hardware single instruction step the function of single stepping one cpu instruction is performed by using a breakpoint range over the code to be single stepped. the dcu includes a mechanism to prevent the breakpoint trap han- dler single-stepping itself. by selecting an inverse range, the effect of single stepping one high level instruction can be achieved. 14.3.5 jump trace jump tracing monitors code jumps, where a jump is any change in execution fl ow from the stream of consecutive instructions stored in memory. a jump may be caused by a program instruction, an interrupt or a trap. when the jump occurs, a 32-bit dcu register is loaded with the origin of the jump. this value points to the instruction which would have been executed next if the jump had not occurred. the cpu may not have completed the instruction prior to the change in fl ow. the diagnostic controller can be set to trace the origin of each jump, the destination, or both. the dcu copies the details of each jump to a rolling trace buffer in memory. the trace buffer may be located in host memory, but using target memory will have less impact on performance. the tracing facility has two modes: ? low intrusion. in this mode the dcu uses dead memory cycles to write the trace into the buffer. this means that the cpu is not delayed, but some trace information may be lost. ? complete trace. in this mode, the cpu is stalled on every jump to ensure the data can be written to the buffer. this means that no trace information is lost, but the cpu performance is affected. 14.3.6 logic state analyzer (lsa) support two signals, triggerin and triggerout , are provided to support diagnostics with an external lsa. the action by the dcu on receiving a triggerin signal is programmable. the selection of internal events which trigger a triggerout signal is also programmable. 14.3.7 trigger combinations and sequences complex trigger conditions can be programmed. for example: ? the 5th time that breakpoint 3 is encountered; ? enable a watchpoint when a breakpoint occurs. there is no software intrusion imposed by this mechanism.
ST20-GP6 79/123 14.4 controlling the diagnostic controller this section gives a summary of host communications with the diagnostic controller. the diagnostic controller has direct access to: ? the instruction pointer, ? a selection of cpu state control signals, ? the memory bus, ? memory-mapped peripheral confi guration registers. this access does not depend on the state of the cpu. access to non-memory-mapped peripheral confi guration registers is via the cpu, and for this the cpu must be active and running the appro- priate handler. the host can give two commands to the diagnostic controller: peek and poke . peek reads memory locations or confi guration registers, and poke writes to memory locations or confi guration registers. the diagnostic controller responds to a peek command with a peeked message, giving the con- tents of the peeked addresses. the diagnostic controller has registers, which are accessed from the host using peek and poke commands. the registers are used to control breakpoints, watchpoints, datawatch, tracing and other facilities. the target cpu can also access these registers using the normal device load and store instruc- tions, so the target software running on the cpu can program its own diagnostic controller. a lock is provided to prevent cpu access, which can be released by the diagnostic controller when a breakpoint or watchpoint match occurs. in addition, the target cpu can peek and poke the host via the diagnostic controller by reading or writing addresses in the top half of the memory space of the diagnostic controller. this facility can be disabled. various different types of cpu events can be selected as trigger events . when an trigger event occurs, the diagnostic controller can send a triggered message. the four types of message are summarized in table 14.1. the messages are distinguished by the two least signifi cant bits of the message header byte. messages may be initiated from either the host or the target. target initiated messages, which con- stitute asynchronous or unsolicited messages, can be enabled by a property bit. messages are composed of a header byte followed by zero or more data bytes, depending on the type of message. the formats for the four message types are shown in figure 14.2. message type direction bit 1 bit 0 meaning poke command. 0 0 write to one or more addresses. peek command. 0 1 read from one or more addresses. peeked opposite to peek command. 1 0 the result of a peek command. triggered dcu to host. 1 1 a trigger event has occurred. table 14.1 types of diagnostic controller message
ST20-GP6 80/123 : figure 14.2 message formats 14.5 peeking and poking the host from the target the target cpu can peek and poke the host via the diagnostic controller. this is done by reading or writing a single word to a block of addresses within the dcu register block. the dcu will then send a peek or poke message to the host. after a host peek , the target cpu will wait until the host responds with a peeked message, which the dcu returns to the cpu as memory read data. peeking and poking the host from the target can be enabled or disabled. after reset, these bits are cleared, so peek and poke from the target are disabled. 14.6 abortable instructions 14.6.1 properties of the hardware implementation in the st20-c2 core, some instructions are abortable, i.e. they may be astartedo more than once. in the instruction set chapter, abortable instructions are marked with an `a' in the notes column, indi- cating that the instruction can be aborted and later restarted. the breakpoint mechanism in the dcu, follows the cpu behavior, and takes a trap in place of starting an instruction with an iptr which matches. care is taken in the hardware to ensure that any interrupts which might have occurred following the preceding instruction are allowed in, and the trap is taken only if the cpu was about to start the instruction with an iptr which matches. if the dcu is programmed to break on an instruction, then normally, following the trap return instruction, that instruction is executed. in this scenario, all instructions should be considered as abortable. if an interrupt occurs between the end of the trap handler and the start of the instruction, then when the interrupt completes the dcu will again trap on that instruction (if the breakpoint is repeatable). the user needs to be aware that setting a breakpoint on a given instruction may break more than once on the same instruction in the same thread. poke command messages response messages address first data word second data word peek address peeked first data word second data word third data word triggered header header header header
ST20-GP6 81/123 14.6.2 software solutions if the user wishes to break on the n th occurrence of a given instruction using a counter in the dcu, then there is no problem associated with abortable instructions because the counter is adjusted on the completion of the instruction, not the start of the instruction. more specifi cally, the counter is adjusted when the cpu commits to executing the instruction; this may be at the completion of an abortable instruction, or it may be at an interrupt point in the middle of an interruptible instruction. in the more complex example, the user wishes to break on the nth occurrence of a given instruction in a given thread. in this case, a hardware break is set on the given instruction, and the breakpoint trap handler contains just enough code to distinguish the desired thread and decrement a counter in software. of course, inserting the breakpoint makes the instruction appear to be abortable and the count is not reliable. however, if a pair of break points are used, and counting only takes place when the desired thread moves from the fi rst to the second breakpoint, then a reliable count can be established.
ST20-GP6 82/123 15 uart interface (asc) the uart interface, also referred to as the asynchronous serial controller (asc), provides serial communication between the ST20-GP6 and other microcontrollers, microprocessors or external peripherals. the asc supports full-duplex asynchronous communication. eight or nine bit data transfer, parity generation, and the number of stop bits are programmable. parity, framing, and overrun error detection are provided to increase the reliability of data transfers. transmission and reception of data can simply be double-buffered, or16-deep fi fos may be used. for multiprocessor communica- tions, a mechanism to distinguish the address from the data bytes is included. testing is supported by a loop-back option. a 16-bit baud rate generator provides the asc with a separate serial clock signal. 15.1 functionality the asc suppor ts full-duplex asynchronous communication, where both the transmitter and the receiver use the same data frame format and the same baud rate. data is transmitted on the txd pin and received on the rxd pin. data frames 8-bit data frames either consist of: ? eight data bits d0-7 (by setting the mode bit fi eld to 001); ? seven data bits d0-6 plus an automatically generated parity bit (by setting the mode bit fi eld to 011). parity may be odd or even, depending on the parityodd bit in the asccontrol register. an even parity bit will be set, if the modulo-2-sum of the seven data bits is 1. an odd parity bit will be cleared in this case. figure 15.1 8-bit data frames 9-bit data frames either consist of: ? nine data bits d0-8 (by setting the mode bit fi eld to 100); ? eight data bits d0-7 plus an automatically generated parity bit (by setting the mode bit fi eld to 111); ? eight data bits d0-7 plus a wake-up bit (by setting the mode bit fi eld to 101). start bit d0 d1 d2 d3 d4 d5 d6 8th bit (lsb) 1st stop bit 2nd stop bit ? data bit ( d7 ) ? parity bit
ST20-GP6 83/123 parity may be odd or even, depending on the parityodd bit in the asccontrol register. an even parity bit will be set, if the modulo-2-sum of the eight data bits is 1. an odd parity bit will be cleared in this case. in wake-up mode, received frames are only transferred to the receive buffer register if the ninth bit (the wake-up bit) is 1. if this bit is 0, no receive interrupt request will be activated and no data will be transferred. this feature may be used to control communication in multi-processor systems. when the master processor wants to transmit a block of data to one of several slaves, it fi rst sends out an address byte which identifi es the target slave. an address byte differs from a data byte in that the additional ninth bit is a 1 for an address byte and a 0 for a data byte, so no slave will be interrupted by a data byte. an address byte will interrupt all slaves (operating in 8-bit data + wake-up bit mode), so each slave can examine the 8 least signifi cant bits (lsbs) of the received character (the address). the addressed slave will switch to 9-bit data mode, which enables it to receive the data bytes that will be coming (with the wake-up bit cleared). the slaves that are not being addressed remain in 8-bit data + wake-up bit mode, ignoring the following data bytes. figure 15.2 9-bit data frames transmission values to be transmitted are written to the transmit fi fo, txfi fo, by writing to asctxbuffer . the txfi fo is implemented as a 16 deep array of 9 bit vectors. if the fi fos are enabled (the asccontrol(fifoenable) is set), the txfi fo is considered full ( ascsta- tus(txfull) is set) when it contains 16 characters. further writes to asctxbuffer in this situation will fail to overwrite the most recent entry in the txfi fo. if the fi fos are disabled, the txfi fo is consid- ered full ( ascstatus(txfull) is set) when it contains 1 character, and a write to asctxbuffer in this situation will overwrite the contents. if the fi fos are enabled, ascstatus(txhalfempty) is set when the txfi fo contains 8 or fewer char- acters. if the fi fos are disabled, it's set when the txfi fo is empty. writing anything to asctxreset empties the txfi fo. values are shifted out of the bottom of the txfi fo into a 9-bit txshift register in order to be transmit- ted. if the transmitter is idle (the txshift register is empty) and something is written to the asctx- buffer so that the txfi fo becomes non-empty, the txshift register is immediately loaded from the txfi fo and transmission of the data in the txshift register begins at the next baud rate tick. start bit d0 d1 d2 d3 d4 d5 d6 9th bit (lsb) 1st stop bit 2nd stop bit ? data bit ( d8 ) ? parity bit d7 ? wake-up bit
ST20-GP6 84/123 at the time the transmitter is just about to transmit the stop bits, then if the txfi fo is non-empty, the txshift register will be immediately loaded from the txfi fo, and transmission of this new data will begin as soon as the current stop bit period is over (i.e. the next start bit will be transmitted imme- diately following the current stop bit period). thus back-to-back transmission of data can take place. if instead the txfi fo is empty at this point, then the txshift register will become empty. asc- status(txempty) indicates whether the txshift register is empty. after changing the fi foenable bit, it is important to reset the fi fo to empty (by writing to the asctxreset register), since the state of the fifo pointer may be garbage. the loop-back option (selected by the asccontrol(loopback) bit) internally connects the output of the transmitter shift register to the input of the receiver shift register. this may be used to test serial communication routines at an early stage without having to provide an external network. reception reception is initiated by a falling edge on the data input pin ( rxd ), provided that the asccon- trol(run) and asccontrol(rxenable) bits are set. the rxd pin is sampled at 16 times the rate of the selected baud rate. a majority decision of the fi rst, second and third samples of the start bit determines the effective bit value. this avoids erroneous results that may be caused by noise. if the detected value is not a 0 when the start bit is sampled, the receive circuit is reset and waits for the next falling edge transition at the rxd pin. if the start bit is valid, the receive circuit contin- ues sampling and shifts the incoming data frame into the receive shift register. for subsequent data and parity bits, the majority decision of the seventh, eighth and ninth samples in each bit time is used to determine the effective bit value. for 0.5 stop bits, the majority decision of the third, fourth, and fi fth samples during the stop bit is used to determine the effective stop bit value. for 1 and 2 stop bits, the majority decision of the seventh, eighth, and ninth samples during the stop bits is used to determine the effective stop bit values. for 1.5 stop bits, the majority decision of the fi fteenth, sixteenth, and seventeenth samples during the stop bits is used to determine the effective stop bit value. the effective values received on the rxd pin are shifted into a 10-bit rxshift register. the receive fi fo, rxfi fo, is implemented as a 16 deep array of 10-bit vectors (each 9 down to 0). if the rxfi fo is empty, ascstatus(rxbuffull) is set to `0'. if the rxfi fo is not empty, a read from ascrx- buffer will get the oldest entry in the rxfi fo. if fi fos are disabled, the rxfi fo is considered full when it contains one character. ascstatus(rxfifonearfull) is set when the rxfi fo contains more than 8 characters. writing anything to ascrxreset empties the rxfi fo. as soon as the effective value of the last stop bit has been determined, the content of the rxshift register is transferred to the rxfi fo (unless we're in wake-up mode, in which case this happens only if the wake-up bit, bit8, is a `1'). the receive circuit then waits for the next start bit (falling edge tran- sition) at the rxd pin. ascstatus(overrunerror) is set when the rxfi fo is full and a character is loaded from the rxshift register into the rxfifo. it is cleared when the ascrxbuffer register is read.
ST20-GP6 85/123 the most signifi cant bit of each rxfi fo entry (rxfi fo[x][9]) records whether or not there was a frame error when that entry was received (i.e. one of the effective stop bit values was '0'). ascsta- tus(frameerror) is set when at least one of the valid entries in the rxfi fo has its msb set. if the mode is one where a parity bit is expected, then the next bit, rxfi fo[x][8], records whether there was a parity error when that entry was received. note, it does not contain the parity bit that was received. ascstatus(parityerror) is set when at least one of the valid entries in the rxfi fo has bit 8 set. after changing the fi foenable bit, it is important to reset the fi fo to empty (by writing to the ascrxreset register), since the state of the fifo pointers may be garbage. reception is stopped by clearing the asccontrol(rxenable) bit. a currently received frame is completed including the generation of the receive status fl ags. start bits that follow this frame will not be recognized. 15.2 timeout mechanism the asc contains an 8-bit timeout counter. this reloads from asctimeout whenever one or more of the following is true ? ascrxbuffer is read ? the asc is in the middle of receiving a character ? asctimeout is written to if none of these conditions hold, the counter decrements towards 0 at every baud rate tick. ascstatus(timeoutnotempty) is'1' exactly whenever the rxfi fo is not empty and the timeout counter is zero. ascstatus(timeoutidle) is `1' exactly whenever the rxfi fo is empty and the timeout counter is zero. the effect of this is that whenever the rxfi fo has got something in it, the timeout counter will decre- ment until something happens to the rxfi fo. if nothing happens, and the timeout counter reaches zero, the ascstatus(timeoutnotempty) fl ag will be set. when the software has emptied the rxfi fo, the timeout counter will reset and start decrementing. if no more characters arrive, when the counter reaches zero the ascstatus(timeoutidle) fl ag will be set. 15.3 baud rate generation the baud rate generator provides a clock at 16 times the baud rate, called the oversampling clock. this clock only ticks if asccontrol(run) is set to'1'. setting this bit to 0 will immediately freeze the state of the ascs transmitter and receiver. this should only be done when the asc is idle.
ST20-GP6 86/123 the baud rate and the required reload value for a given baud rate can be determined by the follow- ing formulae: where: represents the content of the ascbaudrate register, taken as unsigned 16-bit integer, f cpu is the frequency of the cpu. table 15.3 lists various commonly used baud rates together with the required reload values and the rounded deviation errors for an example baud rate with a cpu clock of 32.736 mhz. 15.4 interrupt control the asc has a single interrupt coming out of it, called asc_interrupt . the status bits in the asc- status register determine the cause of the interrupt. asc_interrupt will go high when a status bit is 1 (high) and the corresponding bit in the ascintenable register is 1. note the status register cannot be written to directly by software. the reset mechanism for the sta- tus register is described below. the following diagram illustrates the situation. baud rate reload value (exact) reload value (integer) reload value (hex) deviation error 38400 53.28125 53 35 -0.53% 28800 71.04167 71 47 -0.06% 19200 106.5625 107 6b 0.41% 14400 142.0833 142 8e -0.06% 9600 213.125 213 d5 -0.06% 4800 426.25 426 1aa -0.06% 2400 852.5 853 355 0.06% 1200 1705 1705 6a9 0.00% 600 3410 3410 d52 0.00% 300 6820 6820 1aa4 0.00% 75 27280 27280 6a90 0.00% table 15.3 baud rates baudrate = 16 () = ( 16 x baudrate ) f cpu f cpu
ST20-GP6 87/123 figure 15.4 asc status and interrupt registers 15.4.1 using the asc interrupts when fifos are disabled when fi fos are disabled, the asc provides three interrupt requests to control data exchange via the serial channel: ? txhalfempty is activated when data is moved from asctxbuffer to the txshift register. ? txempty is activated before the stop bit is transmitted. ? rxbuffull is activated when the received frame is moved to ascrxbuffer . for single transfers it is suffi cient to use the transmitter interrupt ( txempty ), which indicates that the previously loaded data has been transmitted, except for the stop bit. for multiple back-to-back transfers using txempty would leave just one stop bit time for the han- dler to respond to the interrupt and initiate another transmission. using the transmit buffer interrupt ( txhalfempty ) to reload transmit data allows the time to transmit a complete frame for the service routine, as asctxbuffer may be reloaded while the previous data is still being transmitted. ascstatus rxbuffull txempty txhalfempty parityerror frameerror overrunerror 0 1 2 3 4 5 timeoutnotempty timeoutidle rxhalffull 6 7 9 txfull 8 ascintenable rxbuffull ie txempty ie txhalfempty ie parityerror ie frameerror ie overrunerror ie timeoutnotempty ie timeoutidle ie rxhalffull ie asc_interrupt
ST20-GP6 88/123 txhalfempty is an early trigger for the reload routine, while txempty indicates the completed transmission of the data fi eld of the frame. therefore, software using handshake should rely on txempty at the end of a data block to make sure that all data has really been transmitted. 15.4.2 using the asc interrupts when fifos are enabled to transmit a large number of characters back to back, the driver routine would write 16 characters to asctxbuffer , then every time a txhalfempty interrupt fi red, it would write 8 more. when it had nothing more to send, a txempty interrupt would tell it when everything has been transmitted. when receiving, the driver could use rxbuffull to interrupt every time a character came in. alter- natively, if data is coming in back-to-back, it could use rxhalffull to interrupt it when there was at least 8 characters in the rxfi fo to read. it would have as long as it takes to receive 8 characters to respond to this interrupt before data would overrun. if less than eight character streamed in, and no more were received for at least a timeout period, the driver could be woken up by one of the two timeout interrupts, timeoutnotempty or timeoutidle . 15.5 asc configuration register s ascbaudrate register the ascbaudrate register is the dual-function baud rate generator/reload register. a read from this register returns the content of the timer, writing to it updates the reload register. an auto-reload of the timer with the content of the reload register is performed each time the ascbaudrate register is written to. however, if the run bit of the asccontrol register, see table 15.4, is 0 at the time the write operation to the ascbaudrate register is performed, the timer will not be reloaded until the first cpu clock cycle after the run bit is 1. ascbaudrate asc base address + #00 read/write bit bit field write function read function 15:0 reloadval 16-bit reload value 16-bit count value table 15.1 ascbaudrate register format
ST20-GP6 89/123 asctxbuffer register writing to the transmit buffer register starts data transmission. asctxbuffer asc base address + #04 write only bit bit field function 0 td0 transmit buffer data d0 1 td1 transmit buffer data d1 2 td2 transmit buffer data d2 3 td3 transmit buffer data d3 4 td4 transmit buffer data d4 5 td5 transmit buffer data d5 6 td6 transmit buffer data d6 7 td7/parity transmit buffer data d7 , or parity bit - dependent on the operating mode (the setting of the mode fi eld in the asccontrol register). 8 td8/parity /wake/0 transmit buffer data d8 , or parity bit, or wake-upbit or undefi ned - dependenton the operating mode (the setting of the mode fi eld in the asccontrol register). note: if the mode fi eld selects an 8-bit frame then this bit should be written as 0. 15:9 reserved. write 0. table 15.2 asctxbuffer register format
ST20-GP6 90/123 ascrxbuffer register the received data and, if provided by the selected operating mode, the received parity bit can be read from the receive buffer register. asccontrol register this register controls the operating mode of the asc and contains control bits for mode and error check selection, and status fl ags for error identifi cation. note : programming the mode control fi eld ( mode ) to one of the reserved combinations may result in unpredictable behavior. note : serial data transmission or reception is only possible when the baud rate generator run bit ( run ) is set to 1. when the run bit is set to 0, txd will be 1. setting the run bit to 0 will immedi- ately freeze the state of the transmitter and receiver. this should only be done when the asc is idle. ascrxbuffer asc base address + #08 read only bit bit field function 0 rd0 receive buffer data d0 1 rd1 receive buffer data d1 2 rd2 receive buffer data d2 3 rd3 receive buffer data d3 4 rd4 receive buffer data d4 5 rd5 receive buffer data d5 6 rd6 receive buffer data d6 7 rd7/parity receive buffer data d7 , or parity bit - dependent on the operating mode (the setting of the mode bit in the asccontrol register). 8 rd8/parity/ wake/x receive buffer data d8 , or parity bit, or wake-up bit - dependent on the operating mode (the setting of the mode fi eld in the asccontrol register). note: if the mode fi eld selects a 7- or 8-bit frame then this bit is undefi ned. software should ignore this bit when reading 7- or 8-bit frames. 15:9 reserved. will read back 0. table 15.3 ascrxbuffer register format
ST20-GP6 91/123 asccontrol asc base address + #0c read/write bit bit field function 2:0 mode asc mode control mode2:0 mode 000 reserved 001 8-bit data 010 reserved 011 7-bit data + parity 100 9-bit data 101 8-bit data + wake up bit 110 reserved 111 8-bit data + parity 4:3 stopbits number of stop bits selection stopbits1:0 number of stop bits 00 0.5 stop bits 01 1 stop bit 10 1.5 stop bits 11 2 stop bits 5 parityodd parity selection 0 even parity (parity bit set on odd number of `1's in data) 1 odd parity (parity bit set on even number of `1's in data) 6 loopback loopback mode enable bit 0 standard transmit/receive mode 1 loopback mode enabled 7 run baud rate generator run bit 0 baud rate generator disabled (asc inactive) 1 baud rate generator enabled 8 rxenable receiver enable bit 0 receiver disabled 1 receiver enabled 10 fifoenable fifo enable bit 0 fifo mode disabled 1 fifo mode enabled 15:11, 9 reserved. write 0, will read back 0. table 15.4 asccontrol register format
ST20-GP6 92/123 ascintenable register the ascintenable register enables a source of interrupt. interrupts will occur when a status bit in the ascstatus register is 1, and the corresponding bit in the ascintenable register is 1.* ascintenable asc base address + #10 read/write bit bit field function 0 rxbuffullie receiver buffer full interrupt enable 1 txemptyie transmitter empty interrupt enable 2 txhalfemptyie transmitter buffer half empty interrupt enable 3 parityerrorie parity error interrupt enable 4 frameerrorie framing error interrupt enable 5 overrunerrorie overrun error interrupt enable 6 timeoutnotempty ie timeout not empty interrupt enable 7 timeoutidleie timeout idle interrupt enable 8 rxhalffullie receiver buffer half full interrupt enable 15:9 reserved. write 0, will read back 0. table 15.5 ascintenable register format
ST20-GP6 93/123 ascstatus register the ascstatus register determines the cause of an interrupt. timeout register the timeout register determines the timeout period. ascstatus asc base address + #14 read only bit bit field function 0 rxbuffull set when rxfi fo not empty 1 txempty set when transmit shift register is empty 2 txhalfempty set when txfi fo at least half empty 3 parityerror set when the rxfi fo contains something received with a parity error 4 frameerror set when the rxfi fo contains something received with a frame error 5 overrunerror set when data is received and the rxfi fo is full. 6 timeoutnotempty set when there's a timeout and the rxfi fo is not empty 7 timeoutidle set when there's a timeout and the rxfi fo is empty 8 rxhalffull set when the rxfi fo contains at least 8 characters 9 txfull set when the txfi fo contains 16 characters 15:10 reserved. read back 0. table 15.6 ascstatus register format asctimeout asc base address + #1c read/write bit bit field function 7:0 timeout timeout period in baud rate ticks 15:8 reserved. write 0, will read back 0. table 15.7 asctimeout register format
ST20-GP6 94/123 16 parallel input/output the ST20-GP6 device has 16 bits of parallel input/output (pio), confi gured in groups (ports) of eight bits. each bit is programmable as an output, an input, or a bidirectional pin. each group of eight input bits can also be compared against a register and an interrupt generated when the value is not equal. each of the groups of eight bits operates as described in the following section. 16.1 pio ports0-1 each of the eight bits of a pio port has a corresponding bit in the pio registers associated with each port. these registers hold: output data for the port ( pout ); the input data read from the pin ( pin ); pio bit confi guration register ( pc1 ); and the two input compare function registers ( pcomp and pmask ). all of the registers, except the pin registers, are each mapped onto two additional addresses so that bits can be set or cleared individually. the set_ register allows bits to be set individually. writing a `1' in this register sets the correspond- ing bit in the associated register, a `0' leaves the bit unchanged. the clear_ register allows bits to be cleared individually. writing a `1' in this register resets the cor- responding bit in the associated register, a `0' leaves the bit unchanged. 16.1.1 pio data registers the base addresses for the pio registers are given in the memory map. note that during reset all the registers are reset to '00000000'. pout register this register holds output data for the port. pin register the data read from this register will give the logic level present on an input pin of the port at the start of the read cycle to this register. the read data will be the last value written to the register regardless of the pin configuration selected. pout pio base address + #00 read/write bit bit field function 7:0 pout7:0 bits 0 to 7 of output data for the port. table 16.1 pout register format - 1 register per port pin pio base address + #10 read only bit bit field function 7:0 pin7:0 bits 0 to 7 of input data for the port. table 16.2 pin register format - 1 register per port
ST20-GP6 95/123 16.1.2 pio bit configuration register the pc1 register is used to confi gure each of the pio port bits as an input or output. writing a 0 confi gures the bit as an input, a 1 configures the bit as an output. 16.1.3 pio input compare and compare mask registers the input compare register ( pcomp ) holds the value to which the input data from the pio ports pins will be compared. if any of the input bits are different from the corresponding bits in the pcomp register and the corresponding bit position in the pio compare mask register ( pmask )is set to 1, then the internal interrupt signal for the port will be set to 1. the compare function is sensitive to changes in levels on the pins and so the change in state on the input pin must be greater in duration than the interrupt response time for the compare to be seen as a valid interrupt by an interrupt service routine. note that the compare function is operational in all confi gurations for a pio bit including the alter- nate function modes. pc1 pio port base address + #30 read/write bit bit field function 7:0 configdata7:0 confi gures the pio bit as an input or an output. 0 input 1 output table 16.3 pc1 register format pcomp pio base address + #50 read/write bit bit field function 7:0 pcomp7:0 bit 0 to 7 value to which the input data from the pio port pins will be compared. table 16.4 pcomp register format - 1 register per port pmask pio base address + #60 read/write bit bit field function 7:0 pmask7:0 when set to 1, the compare function for the internal interrupt for the port is enabled. if the respective bit (0 to 7) of the input is different to the respective pcomp7:0 bit in the pcomp register, then an interrupt is generated. table 16.5 pmask register format
ST20-GP6 96/123 17 configuration register ad dresses this chapter lists all the ST20-GP6 confi guration registers and gives the addresses of the registers. the complete bit format of each of the registers and its functionality is given in the relevant chapter. the emi and dcu registers can only be accessed using memory instructions. all other registers can be accessed and set by the devlw (device load word) and devsw (device store word) instructions. register address size read/write emiconfigdata0bank0 #00002000 16 r/w emiconfigdata1bank0 #00002004 16 r/w emiconfigdata2bank0 #00002008 16 r/w emiconfigdata3bank0 #0000200c 16 r/w emiconfigdata0bank1 #00002010 16 r/w emiconfigdata1bank1 #00002014 16 r/w emiconfigdata2bank1 #00002018 16 r/w emiconfigdata3bank1 #0000201c 16 r/w emiconfigdata0bank2 #00002020 16 r/w emiconfigdata1bank2 #00002024 16 r/w emiconfigdata2bank2 #00002028 16 r/w emiconfigdata3bank2 #0000202c 16 r/w emiconfigdata0bank3 #00002030 16 r/w emiconfigdata1bank3 #00002034 16 r/w emiconfigdata2bank3 #00002038 16 r/w emiconfigdata3bank3 #0000203c 16 r/w emiconfigloc kbank0 #00002040 1 w emiconfigloc kbank1 #00002044 1 w emiconfigloc kbank2 #00002048 1 w emiconfigloc kbank3 #0000204c 1 w emiconfigstatus #00002050 8 r dcustatus #00003000 13 r dcucontrol #00003004 15 r/w dcusignalling #00003008 24 r/w dcutiproperties #0000300c 21 r/w dcubp1 #00003020 32 r/w dcubp2 #00003024 32 r/w dcubp1&2properties #0000302c 22 r/w dcubc3 #00003040 32 r/w dcubc4 #00003044 32 r/w table 17.1 ST20-GP6 confi guration register addresses
ST20-GP6 97/123 dcubc3&4properties #0000304c 25 r/w dcuwplower #00003060 32 r/w dcuwpupper #00003064 32 r/w dcuwpaddress #00003068 32 r dcuwpproperties #0000306c 25 r/w dcujtiptr #00003080 32 r dcujtfrom #00003084 32 r dcujtaddress #00003088 32 r/w dcujtproperties #0000308c 27 r/w dcuhostmemviatap #00003800 - #00003ffc 32 r/w handlerwptr0 #20000000 32 r/w handlerwptr1 #20000004 32 r/w handlerwptr2 #20000008 32 r/w handlerwptr3 #2000000c 32 r/w handlerwptr4 #20000010 32 r/w handlerwptr5 #20000014 32 r/w handlerwptr6 #20000018 32 r/w handlerwptr7 #2000001c 32 r/w triggermode0 #20000040 3 r/w triggermode1 #20000044 3 r/w triggermode2 #20000048 3 r/w triggermode3 #2000004c 3 r/w triggermode4 #20000050 3 r/w triggermode5 #20000054 3 r/w triggermode6 #20000058 3 r/w triggermode7 #2000005c 3 r/w pending a #20000080 5 r/w set_pending #20000084 5 w clear_pending #20000088 5 w mask #200000c0 17 r/w set_mask #200000c4 17 w clear_mask #200000c8 17 w exec b #20000100 5 r/w set_exec #20000104 5 w clear_exec #20000108 5 w lptimerls #20000400 32 r/w lptimerms #20000404 32 r/w register address size read/write table 17.1 ST20-GP6 confi guration register addresses
ST20-GP6 98/123 lptimerstart c #20000408 1 r/w lpalarmls #20000410 32 r/w lpalarmms #20000414 8 r/w lpalarmstart #20000418 1 r/w lpsyspll #20000420 2 r/w sysratio #20000500 6 r int0priority #20001000 3 r/w int1priority #20001004 3 r/w int2priority #20001008 3 r/w int3priority #2000100c 3 r/w int4priority #20001010 3 r/w int5priority #20001014 3 r/w int6priority #20001018 3 r/w int7priority #2000101c 3 r/w inputinterrupts #20001048 18 r intactivehigh #2000104c 2 r/w intlpenable #20001050 2 r/w rtcweeks #20002000 16 r/w rtcmilliseconds #20002004 30 r/w rtcload #20002008 4 w rtcstatus 2r wdtcleara #20002010 4 w wdtclearb #20002014 4 w wdtstatus #20002018 1 r asc0baudrate #20004000 16 r/w asc0txbuffer #20004004 16 w asc0rxbuffer #20004008 16 r asc0control #2000400c 16 r/w asc0intenable #20004010 8 r/w asc0status #20004014 8 r asc1baudrate #20006000 16 r/w asc1txbuffer #20006004 16 w asc1rxbuffer #20006008 16 r asc1control #2000600c 16 r/w asc1intenable #20006010 8 r/w asc1status #20006014 8 r p0out #20008000 6 r/w set_p0out #20008004 6 w register address size read/write table 17.1 ST20-GP6 confi guration register addresses
ST20-GP6 99/123 clear_p0out #20008008 6 w p0in #20008010 6 r p0c1 #20008030 6 r/w set_p0c1 #20008034 6 w clear_p0c1 #20008038 6 w p0comp #20008050 6 r/w set_p0comp #20008054 6 w clear_p0comp #20008058 6 w p0mask #20008060 6 r/w set_p0mask #20008064 6 w clear_p0mask #20008068 6 w p1out #2000a000 6 r/w set_p1out #2000a004 6 w clear_p1out #2000a008 6 w p1in #2000a010 6 r p1c1 #2000a030 6 r/w set_p1c1 #2000a034 6 w clear_p1c1 #2000a038 6 w p1comp #2000a050 6 r/w set_p1comp #2000a054 6 w clear_p1comp #2000a058 6 w p1mask #2000a060 6 r/w set_p1mask #2000a064 6 w clear_p1mask #2000a068 6 w prncode0 #2000c000 7 w prncode1 #2000c004 7 w prncode2 #2000c008 7 w prncode3 #2000c00c 7 w prncode4 #2000c010 7 w prncode5 #2000c014 7 w prncode6 #2000c018 7 w prncode7 #2000c01c 7 w prncode8 #2000c020 7 w prncode9 #2000c024 7 w prncode10 #2000c028 7 w prncode11 #2000c02c 7 w prnphase0 #2000c040 19 w prnphase0wren 1r register address size read/write table 17.1 ST20-GP6 confi guration register addresses
ST20-GP6 100/123 prnphase1 #2000c044 19 w prnphase1wren 1r prnphase2 #2000c048 19 w prnphase2wren 1r prnphase3 #2000c04c 19 w prnphase3wren 1r prnphase4 #2000c050 19 w prnphase4wren 1r prnphase5 #2000c054 19 w prnphase5wren 1r prnphase6 #2000c058 19 w prnphase6wren 1r prnphase7 #2000c05c 19 w prnphase7wren 1r prnphase8 #2000c060 19 w prnphase8wren 1r prnphase9 #2000c064 19 w prnphase9wren 1r prnphase10 #2000c068 19 w prnphase10wren 1r prnphase11 #2000c06c 19 w prnphase11wren 1r ncofrequency0 #2000c080 18 w ncofrequency1 #2000c084 18 w ncofrequency2 #2000c088 18 w ncofrequency3 #2000c08c 18 w ncofrequency4 #2000c090 18 w ncofrequency5 #2000c094 18 w ncofrequency6 #2000c098 18 w ncofrequency7 #2000c09c 18 w ncofrequency8 #2000c0a0 18 w ncofrequency9 #2000c0a4 18 w ncofrequency10 #2000c0a8 18 w ncofrequency11 #2000c0ac 18 w ncophase0 #2000c0c0 7 w nco1phase #2000c0c4 7 w ncophase2 #2000c0c8 7 w ncophase3 #2000c0cc 7 w register address size read/write table 17.1 ST20-GP6 confi guration register addresses
ST20-GP6 101/123 ncophase4 #2000c0d0 7 w ncophase5 #2000c0d4 7 w ncophase6 #2000c0d8 7 w ncophase7 #2000c0dc 7 w ncophase8 #2000c0e0 7 w ncophase9 #2000c0e4 7 w ncophase10 #2000c0e8 7 w ncophase11 #2000c0ec 7 w prninitialval0 #2000c100 10 w prninitialval1 #2000c104 10 w dspcontrol #2000c140 4 w a. set by interrupt trigger. cleared by interrupt grant. b. set by interrupt valid. cleared by interrupt done. c. cleared by a write to lptimerls or lptimerms register. register address size read/write table 17.1 ST20-GP6 confi guration register addresses
ST20-GP6 102/123 18 electrical specifications absolute maximum ratings operation beyond the absolute maximum ratings may cause permanent damage to the device. all voltages are measured referred to gnd . notes 1 for a package junction to case thermal resistance of 14 c/w. 2 for reliability reasons the long-term current from any pin may be limited to a lower value than stated here. symbol parameter min max units notes v dd dc power supply -0.5 4.5 v v ddrtc voltage at rtcvdd pin referred to gnd -0.5 4.5 v t s storage temperature (ambient) -55 125 c t j temperature under bias (junction) -40 125 c1 i o continuous dc output current from any output pin. -20 20 ma 2 v i applied voltage to all functional pins excluding lowpower- clockin, and notrst pins. -0.5 v dd + 0.5 v v irtc applied voltage to lowpowerclockin and notrst pins. -0.5 v ddrtc + 0.5 v v o voltage on bi-directional and output pins except notmemce . -0.5 v dd + 0.5 v v ortc voltage on the lowpowerclockosc pin -0.5 v ddrtc + 0.5 v pd max power dissipation in package 2.0 w table 18.1 absolute maximum ratings
ST20-GP6 103/123 operating conditions notes 1 for a package junction to case thermal resistance of 14 c/w. 2 the nominal input clock frequency must be 16.368 mhz for the dsp module to function cor- rectly with the gps satellites. symbol parameter min max units notes t a ambient operating temperature of case -40 85 c t j operating temperature of junction -40 125 c1 v i applied voltage to all functional input pins and bidirectional pins excluding lowpowerclockin and notrst pins. 0v dd v v irtc applied voltage to lowpowerclockin and notrst pins 0 v ddrtc v f clk clockin frequency 16.5 mhz 2 c l load capacitance per pin 50 pf table 18.2 operating conditions
ST20-GP6 104/123 dc specifications symbol parameter min typical max units notes v dd positive supply voltage during normal operation. 3.0 3.3 3.6 v v ddoff positive supply voltage when device is off but real time clock is running. -0.3 0 0.3 v v ddrtc voltage at rtcvdd pin referred to gnd . 2.4 3.3 3.6 v normal operation v ddrtc voltage at rtcvdd pin referred to gnd . 1.4 3.3 3.6 v vddoff, notrst set to 1 v dddiff v dd -v ddrtc during normal operation and notrst set to 1. -0.6 0 0.6 v 1 v ih input logic 1 for cmos pins a (except notrst pin) and ttl pins b . a. cmos pins: lowpowerclockin, lowpowerclockosc, lowpowerstatus, notwdreset, wdenable, clockin, speedselect0-1, notrst, triggerout, triggerin, interrupt0-1, enableintrom, buswidth, txd0-1, rxd0-1, pio0[0-7] and pio1[0-7], tdi, tms, tck, nottrst, tdo, gpsif. b. ttl pins: memaddr1-19, memdata0-15, memwait, memreadnotwrite, notmemoe, notmemce0-3, notmembe0-1 2.0 v dd + 0.5 v input logic 1 for notrst pin. 2.4 vdd + 0.5 v v il input logic 0 for cmos pins. input logic 0 for ttl pins. -0.5 -0.5 0.8 0.8 i in input current to input pins. -10 10 m a i oz off state digital output current. -50 50 m a v ohdc output logic 1 2.4 v dd v2 v oldc output logic 0 0 0.4 2 c in input capacitance (input only pins). 4 10 pf c out output capacitance and capacitance of bidirectional pins. 615 pf p op operational power consumption under heavy device activity. fclk of 16.368 mhz and speedselect set to pll operation (x1). no external memory used. 100mw 1w 3 p app operational power consumption under `typical' device activity. fclk of 16.368 mhz and speedselect set to pll operation (x2). external memory used. 150mw 1w 3 p stby operational power during stand-by. 10mw mw 4 p rtc operational power for the real time clock and 16k ram, supplied through the rtcvdd pin. 40 m w m w5 table 18.3 dc specifi cation
ST20-GP6 105/123 notes 1 this is the static specifi cation to ensure low current. 2 output load of 2ma on all pins except pio. output load of 4ma on pio. 3 excludes power used to drive external loads. includes operation of the 32 khz watch crys- tal oscillator. 4 device operation suspended by use of the low power controller with vdd and rtcvdd within specifi cation. frequency of system clock (fclk) is 16.368 mhz and frequency of low power clock is 32768 hz. 5 with rtcvdd at 2.4 v and vdd at 0 v. all inputs static except lowpowerclockin and lowpowerclockosc , frequency of low power clock 32768 hz. all other inputs must be in the range -0.1 to 0.1 v. analogue specifications lowpowerclockin and lowpowerclockosc analogue pins are dedicated low power pins and should only be connected as in figure 13.1 on page 74. due to their high impedance, they must not be monitored or loaded by test equipment. ac specifications notes 1 the maximum is only a guideline to ensure a low current consumption during the change in vdd . 2 the transition need not be monotonic, providing that the notrst pin is forced low during the whole period while the main vdd voltage is not within limits set in the dc operating conditions. symbol parameter min typical max units notes t vddr rise time of vdd during power up (measured between 0.3 v and 2.7 v). 5 ns 100 ms 1, 2 t vddf fall time of vdd during power down (measured between 2.7 v and 0.3 v). 5 ns 100 ms 1, 2 table 18.4 ac specifi cation
ST20-GP6 106/123 19 gps performance this chapter details the performance of a ST20-GP6 based gps receiver. note that the performance is dependent on the quality of the user radio, antenna and software used to track the signal and to calculate the resultant position. 19.1 accuracy 19.1.1 benign site the accuracy performance of a gps receiver is dependent on external factors, in particular the deliberate degradation of the signal by the us dod, known as selective availability (sa). this results in an error specification of 100m. if signal errors are corrected by differential gps, the ST20-GP6 can achieve better than 1m accuracy with 1-second rate corrections. note that the ST20-GP6 supports the rtca-sc159 provided corrections with no additional hardware. for surveying use, the resolution of the counters used in the phase/frequency tracking allows resolution down to 1mm. 19.1.2 under harsh conditions under harsh conditions, accuracy degrades due to: ? noise on the weakened signal ? refl ected signals from buildings and cliffs ? obstruction of satellites the ST20-GP6 pays a 2 db signal/noise ratio penalty by using 1-bit signal coding, there are then no further losses in the signal processing hardware. the fast sampling rate, with both in-phase and quadrature channels, results in the subsequent processing being 11 db better, on a signal to noise ratio, than earlier systems that sample at 2 mhz. thus there is a 9 db overall improvement. accuracy stand alone with selective availability without selective availability < 100m < 30m differential < 1m surveying < 1cm table 19.1 accuracy performance
ST20-GP6 107/123 19.2 time to fir st fix condition receiver situation time to fir st fix autonomous start the receiver has no estimate of time/date/position and no recent almanac 90s cold start the receiver has estimated time/date/position and almanac 45s warm start the receiver has estimated time/date/position and almanac and still valid ephemeris data 7s obscuration the receiver has precise time (to m s level) as its calibrated clock is not stopped 1s table 19.2 time to first fi x
ST20-GP6 108/123 20 timing specifications 20.1 emi timings the `reference clock' used in the emi timings is a virtual clock and is defi ned as the point at which all emi strobe and address outputs programmed to change at the start of a memory cycle have become valid. this is designed to remove process dependent skews from the datasheet descrip- tion and highlight the dominant infl uence of address and strobe timings on memory system design. table 20.1 emi cycle timings notes : 1 memreadnotwrite strobe e not applicable as it does not change state mid cycle. 2 timed relative to the end of the access cycle. there could be many clocks in the access cycle, and the strobes may be programmed to go inactive at a previous clock cycle. symbol parameter min max units notes t chav reference clock high to address valid -9 0 ns t clsv reference clock low to strobe valid -11 3 ns 1 t chsv reference clock high to strobe valid -9 0 ns t rdvch read data valid to reference clock high 10 ns 2 t chrdx read data hold after reference clock high 0 ns 2 t svrdx read data hold after strobe valid 0 ns t chwdv reference clock high to write data valid 2 ns t wvch memwait valid to reference clock high 20 ns t chwx memwait hold after reference clock high 0 ns
ST20-GP6 109/123 figure 20.1 emi timings memdata0-15 t rdvch (read) t chwdv t chsv t clsv t chrdx memwait t wvch t chwx t chav reference clock memaddr1-19 notmemce0-3 notmemoe0 notmembe0-1 memreadnotwrite memdata0-15 (write) t svrdx
ST20-GP6 110/123 20.2 reset timings table 20.2 reset timings figure 20.2 reset timings symbol parameter min nom max units notes t rsthrstl notrst pulse width low with a stable vdd 8 clockin notrst vdd 0 3.0 3.3 8 lowpowerclockin cycles 3 lowpowerclockin cycles or 10 ms notrst vdd 0 3.0 3.3 t rsthrstl
ST20-GP6 111/123 20.3 pio timings reference clock in this case means the last transition of any pio signal. notes : 1 load = 50pf figure 20.3 pio timings symbol parameter min max units note t pchpov pio_refclock high to pio output valid -2 0 ns t ior output rise time 7 30 ns 1 t iof output fall time 7 30 ns 1 table 20.3 pio timings pio reference clock pioout t pchpov v pioout
ST20-GP6 112/123 20.4 clockin timings notes 1 clock transitions must be monotonic within the range v ih to v il (see electrical specifi ca- tions chapter 18 on page 102). 2 in timesonemode, excursions from a 50/50 mark-space ratio will map directly into emi phases which will then not be of equal duration. table 20.4 clockin timings figure 20.4 clockin timings 20.4.1 clockin frequency nominal clockin frequency is 16.36800 mhz 50 ppm tolerance. this tolerance relates to the gps system requirements and not for the device to function. symbol parameter min nom max units notes t dcldch clockin pulse width low for pll operation 20 40 ns 1, 2 t dchdcl clockin pulse width high for pll operation 20 40 ns 1, 2 t dcr clockin rise time for pll operation 20 ns 1 t dcf clockin fall time for pll operation 20 ns 1 t gdvch gpsif valid before clock rising edge 20 ns t chgdx gpsif valid after clock rising edge 10 ns 90% 10% t dcr 2.0v 0.8v 1.5v t dcldch t dchdcl t dcf 90% 10% t gdvch t chgdx gpsif
ST20-GP6 113/123 20.5 jtag ieee 1149.1 timings the ieee 1149.1 tap will function at 5 mhz tck with the following timings. all other electrical characteristics of the tap pins are as defi ned in the electrical specifi cations chapter. figure 20.5 ieee 1149.1 tap timings symbol parameter min nom max units tsetup set-up time 10 ns thold hold time 10 ns tprop propagation delay 50 ns table 20.5 ieee 1149.1 tap timings 1.5v 1.5v 1.5v 1.5v tck input signal tck output signal tsetup thold tprop
ST20-GP6 114/123 21 pin list signals names are prefi xed by not if they are active low, otherwise they are active high. supplies interrupts memory low power controller and real time clock pin in/out function vdd power supply gnd ground rtcvdd real time clock and battery-backed sram supply table 21.1 ST20-GP6 supply pins pin in/out function interrupt0-1 in interrupts table 21.2 ST20-GP6 interrupt pins pin in/out function memaddr1-19 out address bus memdata0-15 in/out data bus. data0 is the least significant bit (lsb) and data15 is the most signifi cant bit (msb). memwait in memory cycle extender memreadnotwrite out indicates if current access is a read or a write notmemoe out output enable strobe notmemce0-3 out chip enable strobes one per bank notmembe0-1 out used as byte enable, or memaddr0 on 8-bit bus buswidth in selects 8 or 16-bit bus at reset table 21.3 ST20-GP6 memory pins pin in/out function lowpowerclockin in low power input clock lowpowerclockosc in/out low power clock oscillator lowpowerstatus out low power status notwdreset out watchdog timer reset wdenable in watchdog timer enable table 21.4 ST20-GP6 low power controller and real time clock pins
ST20-GP6 115/123 system services uart parallel io test access port application specific miscellaneous pin in/out function clockin in system input clock speedselect0-1 in speed selectors notrst in reset triggerout out trigger output from dcu triggerin in trigger input to dcu table 21.5 ST20-GP6 system services pins pin in/out function txd0-1 out uart serial data output rxd0-1 in uart serial data input table 21.6 ST20-GP6 uart pins pin in/out function pio0[0-7] in/out pio port 0 pio1[0-7] in/out pio port 1 table 21.7 ST20-GP6 parallel io pins pin in/out function tdi in test data input tms in test mode select tck in test clock nottrst in test logic reset tdo out test data output table 21.8 ST20-GP6 parallel io pins pin in/out function gpsif in gps if input table 21.9 ST20-GP6 application specific pins pin in/out function connecttognd must be connected to gnd table 21.10 ST20-GP6 miscellaneous pins
ST20-GP6 116/123 22 package specifications the ST20-GP6 is available in a 100 pin plastic quad fl at pack (pqfp) package. 22.1 ST20-GP6 package pinout pin pin name i/o 1 pio1<0> i/o 2 pio1<1> i/o 3 pio1<2> i/o 4 pio1<3> i/o 5 pio1<4> i/o 6 vdd 7 pio1<5> i/o 8 pio1<6> i/o 9 pio1<7> i/o 10 gnd 11 speedselect1 i 12 speedselect0 i 13 wdenable i 14 notwdreset o 15 lowpowerstatus o 16 rtcvdd 17 lowpowerclockosc i/o 18 lowpowerclockin i/o 19 notrst i 20 connecttognd i 21 buswidth i 22 notmemce<0> o 23 vdd 24 notmemce<1> o 25 notmemce<2> o 26 notmemce<3> o 27 gnd 28 notmemoe o 29 memreadnotwrite o 30 memwait i table 22.1 ST20-GP6 package pinout
ST20-GP6 117/123 31 memaddr<19> o 32 memaddr<18> o 33 memaddr<17> o 34 memaddr<16> o 35 memaddr<15> o 36 memaddr<14> o 37 memaddr<13> o 38 memaddr<12> o 39 memaddr<11> o 40 vdd 41 gnd 42 memaddr<10> o 43 memaddr<9> o 44 memaddr<8> o 45 memaddr<7> o 46 memaddr<6> o 47 memaddr<5> o 48 memaddr<4> o 49 memaddr<3> o 50 memaddr<2> o 51 memaddr<1> o 52 notmembe<1> o 53 notmembe<0> o 54 memdata<15> i/o 55 memdata<14> i/o 56 vdd 57 memdata<13> i/o 58 memdata<12> i/o 59 memdata<11> i/o 60 gnd 61 memdata<10> i/o 62 memdata<9> i/o 63 memdata<8> i/o 64 memdata<7> i/o 65 memdata<6> i/o pin pin name i/o table 22.1 ST20-GP6 package pinout
ST20-GP6 118/123 66 memdata<5> i/o 67 memdata<4> i/o 68 memdata<3> i/o 69 memdata<2> i/o 70 memdata<1> i/o 71 vdd 72 memdata<0> i/o 73 nottrst i 74 tclk i 75 gnd 76 tms i 77 tdi i 78 tdo o 79 triggerin i 80 triggerout o 81 pio0<0> i/o 82 pio0<1> i/o 83 pio0<2> i/o 84 pio0<3> i/o 85 pio0<4> i/o 86 pio0<5> i/o 87 pio0<6> i/o 88 pio0<7> i/o 89 clockin i 90 vdd 91 gnd 92 gpsif i 93 interrupt<1> i 94 interrupt<0> i 95 rxd<0> i 96 txd<0> o 97 rxd<1> i 98 txd<1> o 99 vdd 100 gnd pin pin name i/o table 22.1 ST20-GP6 package pinout
ST20-GP6 119/123 22.2 100 pin pqfp package dimensions notes 1 lead fi nish to be 60 sn/40 pb solder plate. 2 maximum lead displacement from the notional centre line will be no greater than 0.125 mm. table 22.2 100 pin pqfp package dimensions ref. control dim. mm alternative dim. inches notes min nom max min nom max a - - 3.400 - - 0.134 a1 0.100 - - 0.004 - - a2 2.540 2.800 3.050 0.096 0.110 0.120 b 0.220 - 0.380 0.009 - 0.015 c 0.130 - 0.230 0.005 - 0.009 d 22.950 - 24.150 0.904 - 0.951 d1 19.900 20.000 20.100 0.783 0.787 0.791 d3 - 18.850 - - 0.742 - ref e 16.950 - 18.150 0.667 - 0.715 e1 13.900 14.000 14.100 0.547 0.551 0.555 e3 - 12.350 - - 0.486 - ref e - 0.650 - - 0.026 - bsc g - - 0.100 - - 0.004 k0 -7 0 -7 l 0.650 0.800 0.950 0.026 0.031 0.037 zd - 0.580 - - 0.23 - ref ze - 0.830 - - 0.033 - ref
ST20-GP6 120/123 figure 22.1 100 pin pqfp package dimensions
ST20-GP6 121/123 23 test access port the ST20-GP6 test access port (tap) conforms to ieee standard 1149.1. the tap consists of fi ve pins: tms , tck , tdi , tdo and nottrst . the instruction register is 5 bits long, with no parity, and the pattern a00001o is loaded into the reg- ister during the capture-ir state. there are four defi ned public instructions, see table 23.1. all other instruction codes are reserved. there are three test data registers; bypass , boundary-scan and identification . these registers operate according to 1149.1. the boundary-scan register is not supported on the ST20-GP6. instruction code a a. msb ... lsb; lsb closest to tdo. instruction selected register 0 0 0 0 0 extest boundary-scan 0 0 0 1 0 idcode identifi cation 0 0 0 1 1 sample/preload boundary-scan 1 1 1 1 1 bypass bypass table 23.1 instruction codes
ST20-GP6 122/123 24 device id the identifi cation code for the ST20-GP6 is # m 5196041, where m is a manufacturing revision num- ber reserved by stmicroelectronics. see table 24.1. the identifi cation code is returned by the ldprodid instruction, see table 7.4 on page 42. 25 ordering information for further information contact your local stmicroelectronics sales office. bit 31 bit 0 mask rev st20 family variant stmicroelectronics manufacturers id a a. defi ned as 1 in ieee 1149.1 standard. reserved 0101000110010110000001000001 5196041 table 24.1 identification code device package st20gp6x33s 100 pin plastic quad fl at pack (pqfp) table 25.1 ordering information
ST20-GP6 123/123 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implicat ion or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without no tice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 1998 stmicroelectronics - all rights reserved http://www.st.com stmicroelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. ?

▲Up To Search▲

Price & Availability of ST20-GP6

	To Download ST20-GP6 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .